An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor. ΔΣ Modulator. Electronic Design Automation Laboratory

Transcription

1 Electronic Design Automation Laboratory National Central University Department of Electrical Engineering, Taiwan ( R.O.C) An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor ΔΣ Modulator Electronic Design Automation Laboratory Department of Electrical Engineering National Central University, Taiwan (R.O.C.) Author : Wei-Hsiang Cheng ( Speaker ) Chin-Cheng Cheng Kuo Po-Jen Chen Yi-Min Wang Chien-Nan Liu

2 Outline Introduction Second-Order Delta-Sigma (ΔΣ ) Modulator Our Bottom-Up Extraction Flow for Non-Ideal Effects Experimental Results Conclusions

3 Introduction Digital Blocks Cell-Based Design Flow 007/0/ Mixed-Signal Design Layout Integration erification Transistor Level Post Simulation Analog Blocks Circuit Design/ Simulation Layout Design/ erification Conventional MS Design Flow violate Reduce iteration times Reuse design and IP-Based design Transistor-level simulation is too slow Wei-Hsiang Cheng Behavior-level simulation Higher abstraction Circuit Behavioral Switch erilog RTL RTL Digital Circuit 3

4 Our Bottom-Up Modeling Flow Top-Down Behavior Modeling Not Suitable for IP designs New Design Circuit Specification Architecture HDL or Matlab Behavioral Model Our Modeling flow Suitable for IP designs Top-down flow Top-down Modeling (using erilog-a) Ideal Behavioral Model Existing Designs (such as IPs) Back Annotation Precise Behavioral Model Bottom-up flow Post Layout Simulation (such as HSPICE) Bottom-up Extraction (DC gain, SR... ) 4

5 Outline Introduction Second-Order Delta-Sigma (ΔΣ ) Modulator Top-down Ideal Behavioral Model Our Bottom-Up Extraction Flow for Non-Ideal Effects Experimental Results Conclusions 5

6 Second-Order SC ΔΣ Modulator Five clock signals to control this operation ref _p i _p i _n ref _n nd SC FE Integrator nd SC FE Integrator Quantizer -bit DAC o 6

7 SC FE Integrator Integration mode Architecture Sampling mode Φ off ; Φ, Φ ref on Φ on ; Φ, Φ ref off 7

8 Ideal Behavioral Model SC Integrator Integration mode Time-domain transfer function o C (t C Z-domain transfer function e C (z) i i e i (t n n ) C + T C ) C ref e (z) C ( z) = C z e ref (t e ref = T C T ( ) = C z [ ) e e e [ ( z) ( )] e in out z n + (t n ) = C + [ e (t n + e (z) T (t n ) + T o (t n ) )] e (t n T )] 8

9 Other Circuit Blocks Quantizer Circuit behavior Comparator If + > -, p = H, else p = L Latch If Φ on, o = p, else o = o -bit DAC o Φ Φ ref+ Φ ref- If Φ on, Φ ref+ = ~ o, Φ ref- = o else Φ ref+ = 0, Φ ref- = 0 9

10 Outline Introduction Second-Order Delta-Sigma (ΔΣ ) Modulator Our Bottom-Up Extraction Flow for Non-Ideal Effects Extraction Flow Finite DC Gain & DC-Level Offset Settling Response Switch Thermal Noise Experimental Results Conclusions 0

11 Our Bottom-Up Extraction Flow Execute the bottom-up extraction flow for non-ideal effects Top-down flow Top-down Modeling (using erilog-a) Ideal Behavioral Model Existing Designs (such as IPs) Back Annotation Precise Behavioral Model Bottom-up flow Post Layout Simulation (such as HSPICE) Bottom-up Extraction (DC gain, SR... )

12 Extraction Mode Break the feedback loop of modulator Switch SC integrator to integration mode ref i st SC FE Integrator <Integration Mode> nd SC FE Integrator -bit DAC Quantizer o 007/0/ Wei-Hsiang Cheng

13 Extraction Patterns Give Extraction Patterns Simulation Obtain Key Parameters = DD ref_p + ref_n = DD Δ Δ key parameters (DC gain, SR...) 3

14 Non-Ideal Effects SC integrator seriously affects the performance of ΔΣ modulator Switch Thermal Noise Finite DC Gain + Slew Rate + Finite Bandwidth + DC-Level Offset + Switch Delay 4

15 Extraction Finite DC Gain Extraction patterns : ref =.65 ± 0.4 DC Gain (.8 =.05 st SC Integrator nd SC Integrator SC =.436).5 out_n ref_p out_n =. 8 out_p =.43 6 out_p ref_n = ref_n =.5 ref_p =.0 5 DC Gain (.85 =.05 SC =.77).5 out_n =.8 5 out_p =.7 7 out_n ref_p out_p ref_n =

16 Extraction DC-Level Offset Extraction patterns : ref =.65 ± 0.4 = offset 3.3 st SC Integrator nd SC Integrator out_n =.8 out_p =.436 out_n + DD out_p = = ref_n =.5 ref_p =.0 5 = offset 3.3 out_n =.85 out_p =.7 7 out_n + DD out_p = =

17 Settling Response Include switch delay, finite slew rate ( SR ) and output damping Two extraction patterns Obtain two real SR value One extraction pattern Obtain output damping, switch delay and Max. SR Ideal Settling Response o initial T d_sw st-max T d SR, SR, SR Max nd-max stable t 7

18 Slew Rate Dynamic SR calculation equation SR SR SR I I CL SR = ( SR ) ref ref ref in SRin SR SR SRin ref in ref ref I out SR basic formula ref ref ref I C out L SR SR SR = I I = C I β(in = C L I L tp ( ) ( ) ( ) β I β = I β = ( ref, ref : Extraction Pattern, SR,SR : Extraction alue) ref ref C tn C ref C ) tp tp tp tn tn tn 8

19 Extraction SR Extraction patterns : ref =.65 ± 0.4 /.65 ± 0. ref_p=.0 5 ref_p=.8 5 SR Φ ref_p=. 5 ref_p= M st SC Integrator (50.75M SR_p=94.74 M 94.74M ).05 SR_p=50.75 M ref Input ref SR 9

20 Output Damping ( / ) Second-Order Integrator Transfer Function o(s) = (s) i s C /C ωo + ξω s + ω o Hard to obtain damping ratio ( ξ ) and pole frequency ( ω o ) ξ = Aω π + ln( OS% ) 4 How to obtain overshoot percent (OS%) and period oscillation (T d ) Easier to be measured from the output waveform RefP. E. Allen, D. R. Holberg CMOS Analog Circuit Design nd ed. New York Oxford, 00 o 0 0 = T d π Finite bandwidth effect ξ

21 Output Damping ( / ) Obtain overshoot percent ( OS% ), period oscillation ( T d ) and Max. slew rate ( SR Max ) using one extraction pattern v o OS % max stable = A initial stable st-max initial SR Max st -max max T d = stable nd-max stable RefP. E. Allen, D. R. Holberg CMOS Analog Circuit Design nd ed. New York Oxford, 00 t

22 Extraction Output Damping Extraction patterns : ref =.65 ± 0.5 initial stable SR Max =.39 =.5808 OS% = = 3.08M ( v),max =.605 ( v) 9 ( v),t = 5 0 ( s) ξ = π ( ) + ln OS% 4 π 9 ω0 =. 5 0 ξ T d st SC Integrator nd SC Integrator max stable d stable initial = = ξ ω initial stable SR 0 Max OS% = = = =.50 =.774 T = 9.56M d max stable π π ln ξ ( v),max =.8 ( v) 6 ( v),t = ( s) d stable initial ( OS% ) = =

23 Extraction Switch Delay Extraction patterns : ref =.65 ± 0.5 st SC Integrator nd SC Integrator 0.006u u u u T d_sw =.8n T d_sw = 4n 3

24 Switch Thermal Noise Gaussian random variable = 4kTR on e T df = + (ππ 0 onc s ) [ (t) + e (t)] DC Gain o (t) = i T kt C kt o (t) i (t) + n(t) DC Gain Cs s Thermal Noise Input = n(t): Gaussian random process with μ=0,σ= Ideal Input RefP.Malcovati,S.Brigati, F.Francesconi, F.Maloberti, P.Cusinato, A.Baschirotto, Behavioral modeling of switched-capacitor sigmadelta modulators, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI :Fundamental Theory and Applications, OL. 50, NO. 3, MARCH 003 4

25 Outline Introduction Second-Order Delta-Sigma (ΔΣ ) Modulator Our Bottom-Up Extraction Flow for Non-Ideal Effects Experimental Results Conclusions 5

26 Setup Environment Second-order ΔΣ modulator Implement in TSMC 0.5um TT_3 CMOS process Oversamping ratio (OSR) = 303 Sampling frequency =.5MHz Signal frequency = 0.6 KHz Our developed behavioral model erilog-a language Simulated in Analog Artist (Cadence) using Spectre Use wavescan tool to Show the timing and frequency waveform Calculate Fast Fourier Transform (FFT) and Signal-to-Noise Ratio (SNR) FFT & SNR setup parameters Timing range : 800 ns ~ 6.4 us Signal range : KHz ~.36 KHz Noise range :.559 KHz ~ KHz Sampling point :

27 Timing Waveform 7

28 FFT & SNR ( HSPICE S Ideal ) 8

29 FFT & SNR ( HSPICE S Our ) Simulation time HSPICE : 35 sec. Our model : 49 sec. 9

30 Conclusions Our bottom-up extraction approach is suitable for IP-based design Switch to extraction mode instead of separating into several subblocks Actual loading effects and parasites can be considered automatically Non-ideal effects can be extracted easily using some extraction patterns Can include the following non-ideal effects Finite DC gain & DC-level offset Settling response Thermal noise Our model is very close to HSPICE results with less simulation time. 30

31 Thanks for your attention ~ 3