THE clock driving a digital-to-analog converter (DAC)

Transcription

1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTES II: EXPRESS BRIEFS, VOL. 57, NO. 1, JANUARY The Effects of Flying-Adder Clocks on Digital-to-Analog Converters Ping Gui, Senior ember, IEEE, Zheng Gao, Student ember, IEEE, Chen-Wei Huang, Student ember, IEEE, and Liming Xiu, Senior ember, IEEE Abstract This brief presents the theoretical and simulation results of the effects of flying-adder FA clocks on digital-to-analog converters DACs. A closed-form expression for the frequency spectrum of the DAC output is derived. Analyses show that there exists a lower bound of the clock frequency above which the FA clock does not introduce any additional frequency components in the DAC output. For an FA clock of frequency between the Nyquist frequency and this lower bound, a closed-form expression of the DAC signal-to-distortion ratio is derived. Index Terms Digital-to-analog converter DAC, flying adder FA, frequency spectrum, frequency synthesis, signal-todistortion ratio SDR, time-average frequency. Fig. 1. Comparison between an ideal clock and an FA clock. I. INTRODUCTION THE clock driving a digital-to-analog converter DAC plays an important role in determining the DAC output characteristics, such as the output waveform distortion and signal-to-distortion ratio SDR. Unlike the conventional definition of clock frequency, the concept of time-average frequency TAF removes the constraint that every clock cycle must have the same length [1], [2]. This TAF concept has led to frequency synthesis architectures that are capable of generating almost arbitrary frequencies with very high frequency resolution. The flying-adder FA-based clock synthesizer is one of the latest developments in the area of on-chip clock synthesis employing the TAF concept [3], [4]. In the fractional mode, the FA clock is made of two cycles with unequal lengths, and the difference in cycle length is determined by the delay of one delay stage, which is denoted as Δ, of the voltage-controlled ring oscillator in the FA phase-locked loop PLL [3]. Fig. 1 shows the FA clock in the fractional mode compared with the ideal clock. The FA clock consists of two different cycles T 1 and T 2,but the average cycle length is T as in the ideal clock and T 2 T 1 =Δ. The unequal clock cycle lengths in the FA clock may introduce error in the DAC construction and result in frequency distortion in the analog output. The effects of clock timing error on DACs have been reported in the literature. ost of the studies focus on the effects of stochastic clock jitter on DACs [5] [8]; therefore, the results are not applicable to the FA clock case. Reference [9] discusses anuscript received June 2, 2009; revised September 11, First published January 8, 2010; current version published January 15, This work was supported in part by the Semiconductor Research Corporation. This paper was recommended by Associate Editor J. Li. P. Gui, Z. Gao, and C.-W. Huang are with Southern ethodist University, Dallas, TX USA pgui@smu.edu. L. Xiu was with Texas Instruments Inc., Dallas, TX USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSII Fig. 2. DAC system under study. the effects of deterministic clock jitter on DACs, but the jitter is modeled as a generic sinusoidal form and the results are unnecessarily complex for DACs driven with an FA clock. This brief studies the unique characteristics of the FA clock and incorporates them into the mathematical analyses of its effects on DACs. Concise and closed-form expressions are derived for the DAC output spectrum and the SDR. The results provide mathematical guidelines on the design of DACs driven with an FA clock. Fig. 2 shows a zeroth-order-hold DAC system under study. The data from a digital signal processing DSP unit are fed to the DAC. The DAC constructs an analog signal by holding every input data for one clock cycle. A low-pass filter LPF filters out the high-frequency components and produces the analog output. This brief focuses on the effects of the nonuniform TAF clock on the construction of the DAC analog output. This is different from the analysis on the effects of nonuniform sampling on analog-to-digital converters ADCs presented in [10]. Note that, in the system under study, both the DSP unit and the DAC are controlled by the same FA clock. Since the data are in digital format, as long as the timing closure is satisfied between the DSP and the DAC, there is no information distortion. In other words, there is no sampling error at the input of the DAC in the system under study. In addition, in order not to complicate the analysis with other factors, quantization error is ignored in our analysis. This brief is organized as follows. Section II introduces the mathematical representation of the output of a DAC driven with an FA clock. The fractional part of the frequency control word for the FA clock r assumes a general form of r =1/, where is any integer greater than or equal to 2. Section III presents /$ IEEE

2 2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTES II: EXPRESS BRIEFS, VOL. 57, NO. 1, JANUARY 2010 Fig. 3. Ideal clock, the FA clock, the clock error, and the DAC output error. the mathematical analysis on the frequency spectrum of the DAC output and derives a closed-form expression for SDR. The lower bound of the clock frequency 2 ω d, with ω d being the signal bandwidth and being an integer greater than or equal to 2 that leads to no frequency distortion within ω d in the DAC output is obtained. Section IV presents the simulation results to verify the theoretical analysis, and Section V concludes this brief. II. ATHEATICAL REPRESENTATION OF DAC DRIVEN WITH FA CLOCK WITH r =1/ Let g i t be the DAC function a rectangular pulse from time 0 to T. The ideal DAC output before the LPF can be expressed as f ideal t= xnt g i t t n = xnt g i t nt. To analyze the DAC driven with an FA clock in the fractional mode, we take the following approach: As an illustrative example, in the case where r =1/2, T 1 and T 2 would alternately appear in the FA clock, i.e., the clock cycle pattern is T 1 T 2, and it repeats with a period of 2T, where T is the period of the ideal clock. Fig. 3 shows the clock waveforms and the DAC output. Fig. 3a is the ideal clock with a uniform period T, and Fig. 3b depicts the FA clock with alternating cycles T 1 and T 2. Fig. 3c shows the difference between these two clocks denoted as Clock Error, which is a sequence of narrow pulses of width 1/2Δ repeating every 2T. The pulse in Clock Error is denoted as g e t. To understand the effects of the FA clock on a DAC, we superimpose the DAC output obtained using the ideal clock to the one using an FA clock, as shown in Fig. 3d. The shaded areas are where the two outputs differ and are denoted as errt, which is the DAC output error. As can be observed, errt is a sequence of g e t, with its magnitude modulated by the sampled inputs. Specifically, errt can be represented as errt = x2nt x2n 1 T g e t 2n 1T Δ 2 where Δ=T 2n T 2n 1, 2nT are the times at which the pulse g e t appears, and 1/4Δ is a time shift chosen to center g e t around t =0 for the convenience of mathematical manipulation. 1 Fig. 4. Clock error signal g et as the sum of g mt for the general case of r =1/. The output signal of the DAC is then the sum of the ideal DAC output f ideal and errt, i.e., ft=f ideal t+errt = xnt g i t nt +errt. 3 The same approach can be applied to a more general case where r =1/ and is any integer greater than or equal to 2. In this case, the FA clock pattern is T 1 T 1,...,T 1 T 2, i.e., 1 cycles of T 1, followed by one cycle of T 2.Fig.4 shows the ideal clock and the FA clock with r =1/. g m t, where m =1, 2,..., 1, represents a pulse signal with a width of Δ m, and g e t is the composite of g m t. The clock error between the ideal and FA clocks is then g e t repeating with a period of T. Since T 2 T 1 =Δand T = 1 T 1 + T 2 = T 1 +Δ, the pulsewidth Δ m can be represented as The time shift of each g m t is denoted by Δ m = m Δ/. 4 t n =k + mt 1 2 Δ m 5 where n = k + m, k =0, ±1, ±2,...; m =1, 2,..., 1. The DAC output error errt can then be represented as errt = [x n +1T xnt ] g e t t n = x k + m +1T x k + mt g e t k + mt Δ m. 6 III. SPECTRU AND SDR ANALYSIS FOR r =1/ AND r = 1/ With errt represented as 6, its Fourier transform can be written as 7, shown at the bottom of the next page. Using the following property [11]: 2π e jkω ω = δ Ω ω k 2π

3 GUI et al.: EFFECTS OF FLYING-ADDER CLOCKS ON DIGITAL-TO-ANALOG CONVERTERS 3 equation 7 can be simplified as 1 ERRω = e jω 1 2 Δm G e ω e jωt e k 2π 1 X e jk 2π m ω + k ω s where ω s =2π/T, with ω s being the DAC sampling clock frequency. F ideal ω can be expressed as F ideal ω = 1 T G iω Xω + k ω s. 9 Combining 8 and 9, the Fourier transform of the DAC output driven with an FA clock is F ω = 1 1 T G iω Xω + k ω s + G e ωe jω 1 2 Δm e jωt e k 2π 1 X ω + k ω s e jk 2π m Equation 10 indicates that F ω consists of two parts: The first part is the spectrum of the ideal DAC output, which contains Xω and its replicas at kω s, with the magnitude modulated by G i ω. The second part contains Xω and its replicas at kω s /, with the magnitude modulated by G e ω. Both G i ω and G e ω in 10 are the spectrum of a sinc function, which is represented by the following expressions: G i ω =e jω T 2 2sin ω T 2 /ω 11 G e ω =G ω+g m=2 ω++ G m= ω 2sin ω Δm = 2 e jωmt e jω Δm ω Because the term ω Δ m is small, the following approximation can be applied in 12: sin ω Δ m ω Δ m and e jω Δm Therefore, 12 can be simplified as G e ω = Δ m ejωmt. 13 A. Analysis of SDR for r =1/ Based on 10, the frequency spectrum and SDR of the DAC output can be analyzed as follows: 1 ω s 2ω d : If the clock frequency ω s 2ω d, an LPF with a cutoff frequency ω d is able to filter out all other frequency components, except Xω; hence, the DAC is able to restore the input signal in analog format, with no frequency distortion being introduced by the TAF clock. In other words, for r =1/, as long as ω s 2ω d, the DAC can produce the analog output without introducing any frequency distortion within ω d, even if the clock cycles do not have the same length. Note that 2ω d is times the minimum clock frequency given by the Nyquist theory 2ω d. 2 2ω d ω s 2ω d : In this case, Xω is replicated every kω s /. For simplicity, the input is assumed as a sinusoidal waveform; thus, Xω =2π δω ω d +2π δω + ω d. Substituting Xω into 10, we have F ω = 2π T G iω 2π + e jωt e k 2π 1 δ δω ω d + k ω s G e ω e jω 1 2 Δm ω ω d + k ω s e jk 2π m. 14 Based on 14, SDR can be obtained as 15, shown at the bottom of the next page. Because Δ m is small, we have e jω1/2δ m 1, and 15 can further be simplified as 16, shown at the bottom of the next page. Note that, in 16, mej2πω d/ω s 1 is negligible, compared to 4π 2 sinπω d /ω s /f d Δ. Replacing G i ω with 11 and G e ω with 13 yields 1 SDR = 20 log 10 sinπ/ + 20 log f d Δ 17 Equation 17 expresses SDR as a function of, Δ, and f d, where f ωd = ω d /2π for the case of 2ω d ω s 2 ω d.the smaller the Δ and f d, the higher the SDR. For the case of =2, 17 becomes 1 SDR = 20 log Δ f d Notice that the SDR in 17 and 18 is independent of the clock frequency ω s. Assuming that Δ=50ps, we plot SDR as a function of f d for =2, as shown in Fig. 5. For an ERRω = = 1 2π errt e jωt dt G e ω e jω 1 2 Δ m 1 XΩ e jω ωmt e jω ωk e jωt e jω ωk dω 7

4 4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTES II: EXPRESS BRIEFS, VOL. 57, NO. 1, JANUARY 2010 Fig. 5. SDR versus f d for r =0.5 =2,when2f d f s 4f d,and Δ=50ps. The cross points represent the simulated results. input signal with a bandwidth of f d =6.51 Hz, the SDR is db for 2ω d ω s 4ω d. The cross points in Fig. 5 represent the SDR obtained from simulations for several different f d s. As can be seen, the simulated SDR agrees with the analysis. We simulate the SDR for the following frequency: khz, 763 khz, Hz, Hz, Hz, 12.2 Hz, and 24.4 Hz, and obtain the corresponding SDR as 90.55, 84.47, 78.42, 72.39, 66.36, 60.34, and db. They are almost identical to those obtained using 18, which are 90.52, 84.5, 78.48, 72.43, 66.41, 60.39, and db, respectively. Details of the simulations are covered in Section IV. Based on 17, Fig. 6 plots SDR versus for 2ω d ω s 2 ω d, with Δ=50ps and f d =6.51 Hz. As increases, the pattern T 1 T 1,...,T 1 T 2 in the FA clock repeats with an increasing period T, and the SDR decreases. We also simulate the SDR for two cases of : =2and =8.The simulation results represented by the cross points in Fig. 6 show good matching with the analysis results. Simulations are covered in Section IV. B. Analysis of SDR for r = 1/ When r = 1/, the FA clock pattern becomes T 2 T 2,...,T 2 T 1, where there are 1 cycles of T 2, followed by one cycle of T 1. The clock error, which is the difference between pattern T 2 T 2,...,T 2 T 1 and pattern TT,...,T, has a similar pattern as in Fig. 4. The DAC output error caused Fig. 6. SDR versus =1/r when 2f d f s 2 f d, f d = 6.51 Hz, and Δ=50ps. The cross points represent the simulated results. by the clock error is the same as that in the case of r =1/ ; thus, for r = 1/, we have the same equations for F ω and SDR as in 14 and 17. IV. SIULATED FREQUENCY SPECTRU OF DAC To verify the mathematical analysis, a SimuLink model of a DAC driven with the FA clock is constructed. The inputs to the DAC are the sampled points of a sinusoidal signal, which were sampled with the FA clock of frequency f s. The DAC inputs are represented using a double-precision floating point with 52 mantissa bits; thus, the quantization error at the input of the DAC is negligible. Δ=50ps is used for all simulations. To perform fast Fourier transform FFT on the DAC output with coherent sampling, the sampling frequency is chosen to be 320 GHz, the number of signal cycles is 128, and the sinusoidal signal is of frequency 6.51 Hz. The number of FFT points is Fig. 7 plots the DAC frequency spectrum with r =0.5 = 2 and f d =6.51 Hz. Two cases are studied: 1 f s =6f d = Hz and 2 f s =3f d =19.53 Hz. In case 1, since f s =6f d 2 f d, there are no frequency distortions within the range of f d, which is confirmed in Fig. 7a. In case 2, since f s =3f d < 2 f d, from the analysis in Section II, we know that there will be frequency distortions within the range of 0 f d. Fig. 7b plots the spectrum from 0 to f s /2. It shows that there exists frequency distortion at Hz. This result agrees with 14, because the location of the frequency distortion is F ω k=0 SDR = 20 log 10 F ω k [1,] 2π T G iω = 20 log 10 2π k=1 δω ω d + k ω s + 2π G e ωe jω 1 2 Δ m e jk 2π m G e ωe jω 1 2 Δm e jωt 1 δ ω ω d + k ω s e jωt+k 2π 1 δ ω ω d + k ω s 15 SDR = 20 log 10 k=1 2π T G iω+ 2π G e ω e jωt 1 G e ωe jk 2π m 2π 16 e jωt e k 2π 1

5 GUI et al.: EFFECTS OF FLYING-ADDER CLOCKS ON DIGITAL-TO-ANALOG CONVERTERS 5 Fig. 7. Frequency spectrum of the DAC output, with r =0.5 =1/2 = 2 and f d =6.51 Hz. a f s =6f d.bf s =3f d. given by f d + kf s /2=3.255 Hz, where k =1.Asshown in Fig. 7b, the magnitude of the signal is db, whereas the magnitude of the error is db, which gives an SDR of db. This result is almost identical to the SDR given by 18, which is db, as plotted in Fig. 5. A couple more simulations are performed for different signal frequencies f d to verify 18. These simulation results are included in Fig. 5 to show good agreement with the analyses. Fig. 8 shows the simulation results for r =0.125 = 1/8 =8. Two cases are simulated: 1 f s =24f d = Hz and 2 f s =6f d = Hz. In Fig. 8a, where f s 2 f d =16f d, there are no frequency distortion within the range of 0 f d. In case 2, since f s =6f d < 2 f d, there exist frequency distortions, as shown in Fig. 8b. The locations of the frequency distortions are given by ±f d + kf s /8 in accordance with 14. In Fig. 8b, the frequency distortions from 0 to f s /2 are located at 1.628, 3.255, 8.138, 11.39, 13.02, 16.28, and 17.9 Hz, with the corresponding magnitudes of 60.41, 54.16, 52.04, 60.41, 52.71, 54.16, and db, respectively. The signal tone is located at 6.51 Hz with a magnitude of db. To obtain the SDR from Fig. 8b, we first convert the magnitude of the signal and that of each frequency distortion from the decibel scale to the linear scale, add up the magnitude of all the frequency distortions as the overall distortion, and then compute 20 logsignal/distortion as the SDR. The result of this calculation is 56.8 db, which agrees well with the 57.5 db computed from 17 and plotted in Fig. 6. V. C ONCLUSION We have presented thorough mathematical analyses on the effects of the FA-based TAF clock on DACs. A closed-form expression of the spectrum of the DAC output driven with such a TAF clock has been derived, and a general form of the minimum TAF clock frequency that introduces no frequency distortion in the DAC output has been obtained. Fig. 8. Frequency spectrum of the DAC output with r =0.125 = 1/8 = 8 and f d =6.51 Hz. a f s =24f d.bf s =6f d. For r =1/ and r = 1/, where is any integer greater than or equal to 2, our analyses show that, when f s 2f d, there is no frequency distortion introduced within ω d in the DAC output driven with a TAF clock. For 2f d f s < 2f d, a closed-form expression of the SDR is derived. The SDR is dependent on the signal bandwidth ω d and Δ, where Δ is the small difference in length between the two FA clock cycles. These results are useful in that they give a clear mathematical condition under which no frequency distortion is introduced in a DAC driven with a TAF clock, where the TAF clock cycles do not have the same length; when such condition is not met, a closed-form expression is derived to evaluate the SDR. REFERENCES [1] B. Goldberg, The evolution and maturity of fractional-n PLL synthesis, icrow. J., vol. 39, no. 9, pp , Sep [2] T. A. D. Riley,. A. Copeland, and T. A. Kwasniewski, Delta-sigma modulation in fractional-n frequency synthesis, IEEE J. Solid-State Circuits, vol. 28, no. 5, pp , ay [3] L. Xiu, The concept of time-average-frequency and mathematic analysis of flying-adder frequency synthesis architecture, IEEE Circuits Syst. ag., vol. 8, no. 3, pp , 3rd Quarter [4] L. Xiu, A flying adder on-chip frequency generator for complex SoC environment, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp , Dec [5] K. Doris, A. V. Roermund, and D. Leenaerts, A general analysis on the timing jitter in D/A converters, in Proc. IEEE ISCAS, 2002, pp. I-117 I-120. [6] V. S. Reinhardt, A review of time jitter and digital systems, in Proc. IEEE Int. Freq. Control Symp. Expo., 2005, pp [7] B.-S. Song, Nyquist-Rate ADC and DAC, in Analog Circuits and Devices. Boca Raton, FL: CRC Press, 2003, ch. 7. [8] J. L. Gonzalez and E. Alarcon, Clock-jitter induced distortion in high speed COS switched-current segmented digital-to-analog converters, in Proc. IEEE ISCAS, 2001, pp [9] Y.-C. Jeng, Direct digital synthesizer with jittered clock, IEEE Trans. Instrum. eas., vol. 46, no. 3, pp , Jun [10] Y.-C. Jeng, Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizers, IEEE Trans. Instrum. eas., vol. 37, no. 2, pp , Jun [11] A. Papoulis, The Fourier Integrals and Its Applications. New York: cgraw-hill, 1962, p. 44.