24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL

Transcription

1 24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL John G. Maneatis 1, Jaeha Kim 1, Iain McClatchie 1, Jay Maxey 2, Manjusha Shankaradas 2 True Circuits, Los Altos, CA 1 Texas Instruments, Dallas, TX 2

2 Clock Generator PLLs for ASICs Network Processor Graphics Processor F REF PLL N F OUT I/O Controller Your ASIC Most ASICs PLLs for clock generation, but Use different frequencies and multiplication 2

3 Optimal PLL Design For each F OUT and N, one must adjust loop parameters for both minimum jitter and stability For clock generators (track input clocks) (ω REF = 2π F OUT /N) Loop bandwidth : ω N ~ ω REF /20 Damping factor : ζ ~ 1 Third-order pole : ω C ~ ω REF /2 Circuit parameters (e.g. I CH, R) must vary with F OUT and N! 3

4 Addressing Diverse Specifications Designing a different PLL for each ASIC Easier to meet the specification, but Verifying all designs is difficult and costly Our Goal: One PLL design for all ASICs Only one design needs verification, but Loop parameters must adjust automatically to satisfy wide range of F OUT and N 4

5 Challenges Self-biased PLLs [Maneatis 96] adjust for F OUT Achieve fixed ω N /ω REF and ζ indep. of PVT But, Self-Biased PLLs do NOT adjust for N ω N /ω REF and ζ vary with N (want fixed) ω C /ω REF varies with N (want fixed) This talk extends Self-Biased PLLs for wide ranges of N with a new loop filter network 5

6 Outline Introduction Review of Self-Biased PLLs Pattern Jitter Issues Loop Filter Architecture Implementation of Key Circuits Measured Results Conclusions 6

7 Second-Order PLLs CK REF CK FB PFD UP DN CP I CH C 1 R V CTL VCO K V CK OUT N P O P(s) I (s) = N ζ ζ (s / ω (s / ω N ) + N ) (s / ω N ) 2 1 I K 1 ωn = CH V ζ = ωn R C1 N C

8 Self-Biased PLLs CK REF CK FB PFD UP DN CP x I D CP x I D V FF C 1 V CTL 1/g m I D Replica-Feedback Biasing V BN VCO K V =k/c B CK OUT N R = 1/ g m I CH = x ID F VCO = gm CB 8

9 9 J. G. Maneatis, Presented at ISSCC 2003 Self-Biased PLLs With Self-Biased PLLs ω N /ω REF and ζ are constant with F OUT, BUT not with N N x ~ C C N x B REF N = π ω ω N x ~ C C N x 4 1 B 1 = ζ

10 Pattern Jitter / Spurious Noise Phase corrections every rising reference edge can cause disruptions to nearby output cycles Periodic noise pattern repeats every ref. cycle or N output cycles CK REF V CTL CK OUT SHORT Typical causes Charge pump imbalances or leakage Jitter in reference clock (aperiodic result) 10

11 Shunt Capacitor Use third-order pole to extend disturbance with reduced amplitude over many output cycles CK REF V CTL FILTERED CK OUT Problem with varying N using fixed capacitor Extended number of cycles NOT function of N Too few for large N Pattern jitter Too many for small N Instability 11

12 Proposed Loop Filter Use switched capacitor filter network to Output scaled amplitude error signal with N output cycle duration [Maxim 01] CK REF V CTL FILTERED CK OUT Want a simple solution using this approach that is compatible with Self-Biased PLLs 12

13 Original Filter Network UP DN CP V FF 1/g m V BN CP C 1 Replica-Feedback Biasing V CTL Only need to filter feed-forward path 13

14 Sampled Feed-Forward Network V FF 1/g m UP DN CP C 2 g m V BN CP V RST C 1 V CTL Replica-Feedback Biasing Sample phase error and generate proportional current that is held constant for N T OUT Sampled error is reset at end of ref. cycle Need V RST = V CTL as zero bias level 14

15 Complete Filter Network V FF 1/g m UP DN CP C 2 g m V BN C 1 Replica-Feedback Biasing V CTL Reset C 2 to V CTL directly Eliminates C 1 charge pump Equivalent feed-forward control gain Q O ~ N Q I 15

16 Loop Dynamics With this new loop filter network we achieve ω ω ~ x N ζ ( Q Q ) x N ~ x N N REF ~ O I Need to keep ω N /ω REF and ζ constant with N Just scale charge pump current with 1/N (=x) More detailed analysis will show ω 1 C B C N ωref = 1 2 π ζ = 1 CB C1 C2 4 Both are independent of F OUT, N, and PVT! 16

17 Complete Self-Biased CGPLL Loop Filter UP C 2 g m (V FS1 +V FS2 ) DN CP 1 V FS1 CK REF CK FB PFD V BC C 1 V FF 1/g m V BP V BN VCO CK OUT CP 2 C 2 V FS2 V CTL Replica-Feedback VCO Bias Gen. V BC Charge Pump Bias Gen. (Prog. 1/N Current Mirror) Divide Ratio (N= ) Clock Divider 17

18 Self-Biased Filter Network V FS1 C 2 CP 1 en S 1 V FF V BN UP DN CP 2 en V FS2 S 2 C 2 V BN Select Control C 1 V CTL 18

19 Filter Network Reset Switches V DD +V CTL V CTL V BR V CTL sel_boosted V BN V FS V CTL SEL_B SEL Can switch to V CTL independent of voltage level 19

20 Inverse-Linear Current Mirror Need to generate I CH = I D / N Use switches to adjust device size on input side For N=1~4096, need 12 binary weighted legs Need size range of 2048:1 Too much area! I IN I OUT V BD S 5 S 4 S 3 S 2 S 1 S 0 x32 x16 x8 x4 x2 x1 20

21 Multi-Stage Linear CM Solution to size problem with LINEAR control I IN Use multiple device groups operating at different but ratioed current densities Can have large ranges using small devices I OUT 8:1 V BD S 5 S 4 S 3 S 2 S 1 S 0 x4 x2 x1 x4 x2 x1 21

22 Multi-Stage Inverse-Linear CM Just diode connect multi-stage linear current source and use as input side of current mirror Can output gate bias of any device group Stable as long as gain blocks reduce currents I IN I OUT V BD S 5 8:1 S 4 S 3 S 2 S 1 S 0 x4 x2 x1 x4 x2 x1 22

23 Complete Current Mirror I IN I OUT I IN 1 N I OUT V BN (N = ) V BC V BD S 11 S 10 S 9 S 7 S 6 S 8 S 5 S 4 S 3 S 2 S 1 S 0 E 3 E 2 8:1 E 3 8:1 E 2 8:1 x4 x2 x1 x1 23

24 Voltage-Controlled Oscillator VCO Replica-Feedback Bias Generator Buffer Stage V BP V FF V BP V REP V O - V I + V TAIL V O + V I - V CTL V BN V BN V BP 11-Stage Ring Oscillator CK+ CK- CK- CK+ V BN 24

25 Buffer Tail Node Matching V V REP V V TAIL time I D I L I H V V Higher V DD V DS 25

26 Modified VCO VCO Replica-Feedback Bias Generator Buffer Stage V BP V FF V BP V O - V I + V O + V I - V CTL V BN V BN V TAIL (SHARED) V BP 11-Stage Ring Oscillator CK+ CK- CK- CK+ V TAIL V BN 26

27 Static Supply Sensitivity 27

28 PLL Implementation Process Technology Nominal Supply Voltage Total Occupied Area VCO Frequency Range Multiplication Factor Range Power Dissipation 0.13µm N-well CMOS 1.5V (designed for 1.2V) 0.38 x 0.48mm 2 30 ~ 650 MHz N = 1 ~ MHz, 1.5V PLL Loop Filter Capacitors 28

29 Measured Jitter vs N (240MHz) 29

30 Conclusions Proposed PLL achieves wide N and F OUT range PLL is self-biased with constant loop dynamics (ω N /ω REF, ζ ), independent of N, F OUT, and PVT Sampled feed-forward network suppresses pattern jitter with effective ω C that tracks ω REF Achieves relatively constant period jitter of less than 1.7% as N is scaled from 1 to