LECTURE 090 FILTERS AND CHARGE PUMPS

Size: px
Start display at page:

Download "LECTURE 090 FILTERS AND CHARGE PUMPS"

Transcription

1 Lecture 090 Filters and Charge Pumps (09/01/03) Page 0901 LECTURE 090 FILTERS AND CHARGE PUMPS Objective The objective of this presentation is to examine the circuits aspects of loop filters and charge pumps suitable for PLLs in more detail. Outline Filters Charge Pumps Summary Lecture 090 Filters and Charge Pumps (09/01/03) Page 0902 Why Does the PLL Need a Filter? Input Signal Oscillator Output Signal Phase Frequency Detector FILTERS Error Signal Voltage Controlled Oscillator Loop Filter Contolling Voltage Fig The loop filter is important to the performance of the PLL. 1.) Removes high frequency noise of the detector 2.) Influences the hold and capture ranges 3.) Influences the switching speed of the loop in lock. 4.) Easy way to change the dynamics of the PLL

2 Lecture 090 Filters and Charge Pumps (09/01/03) Page 0903 Passive Loop Filters 1 1.) F(s) = + 1 = s C = sτ1, τ 1 = C 1 sc 1 R sc scr ) F(s) = + R = sc ( + R 2 ) + 1 = sc τ 1 = C( + R 2 ) and τ 2 = R 2 C 1 + sτ sτ 1 C 1 Fig C R 2 Advantages: Linear Relatively low noise Unlimited frequency range Disadvantages: Hard to integrate when the values are large (C>100pF and R > 100kΩ) Difficult to get a pole at the origin (increase the order of the type of PLL) Fig Lecture 090 Filters and Charge Pumps (09/01/03) Page 0904 Active Filters 1.) Active lag filteri R sc 2 F(s) = + 1 = sc 1 = C 1 C 2 C 1 C 2 sr 2 C s C sτ sτ 1 + 1, τ 1 = C 1 and τ 2 = R 2 C 2 C 1 R 2 C 2 Fig ) Active lag filter II 1 R 2 sc 2 R sc 2 F(s) = 1 = R 1 sc sc 1 R 2 s C 1 +1 sr 2 C 2 +1 = R 2 sτ sτ C 1 R 2 C 2 + Fig

3 Lecture 090 Filters and Charge Pumps (09/01/03) Page 0905 Active Filters Continued 3.) Active PI filter. R sc 2 F(s) = = sr 2 C s C 2 sτ = sτ 1 τ 1 = C 2 and τ 2 = R 2 C 2 Advantages: Can get poles at the origin Can reduce the passive element sizes using transresistance We can show that (eq.) = R x Assume = 10kΩ and R x = 10Ω gives (eq.) = 20kΩ + 100,000kΩ 10Ω 10MΩ Disadvantages: Noise Power Frequency limitation R 2 C 2 + V in i x Fig R 2 C 2 + Fig Lecture 090 Filters and Charge Pumps (09/01/03) Page 0906 Active Filters Continued Cancellation of the temperature/voltage dependence on the Tee transresistance: Let R T = R x Differentiate R T with respect to x where x = T or V. dr T dx = 2d dx + 2d R x dx 2 dr x R 2 x dx = d R x dx R 2 1 R dr x 2 x dx Setting the above = 0 and assuming that d dx = dr x dx, gives 2 R 1 R x 2 R x 2 = 0 = 2.732R x R T = R x Design: 1.) Choose R T. 2.) Solve for R x. 3.) Solve for. Example: Let R T = 100kΩ. R x = Check 100kΩ kΩ = 7.735kΩ = R x = kΩ R T = 2(21.132kΩ) kΩ kΩ = 100kΩ

4 Lecture 090 Filters and Charge Pumps (09/01/03) Page 0907 Example 1 Loop Filter (a.) Find the transfer function of the filter shown assuming an ideal op amp. (b.) Sketch a Bode plot for the magnitude of this filter if = R 2 = 10kΩ and C 2 = 0.159µF. (c.) For the values in part (b.), find the single sideband spur at a reference frequency of 25 khz if the op amp has an input offset current of I os = 50nA and an input offset voltage of V io = 100µV. Assume that the spurious deviation due to the offset voltage at 25 khz can be expressed as θ d = 100V pm, where V pm is the phase modulation caused by the offset voltage of the filter. Solution (a.) The transfer function assuming an ideal op amp can be found as, (s) V in (s) = Z 1+Z 2 Z 1 = + R 2 + (1/sC 2 ) = s(+r 2 )C sc 2 (b.) If = R 2 = 10kΩ and C 2 = 0.159µF, then the filter transfer function becomes, F(s) = s(r s 1+R 2 )C sc 2 = s s = s V in C 2 R 2 SU03E2P3 Lecture 090 Filters and Charge Pumps (09/01/03) Page 0908 Example 1 Continued The sketch for the magnitude of this transfer function is below db (c.) Find the offset voltage at the input of the filter, V OS, from the figure shown. V OS = V io + I os = 100µV + 50nA 10kΩ V OS = 0.1mV + 0.5mV = 0.6mV = 600µV θ d = 100V pm = 100(2 V OS ) = 0.12 SSB = 20 log 10 (θ d /2) = dbc Frequency (radians/sec.) SU03E2S3 V OS I os V io C 2 R 2 SU03E2S3B

5 Lecture 090 Filters and Charge Pumps (09/01/03) Page 0909 HigherOrder Active Filters 1.) Cascading firstorder filters (all poles are on the negative real axis) Uses more op amps and dissipates more power. 2.) Extending the laglead filter. V in 2 2 R 2 C 2 C 3 + Fig From the previous slide we can write, sr 1 C 3 Z 1 (s)(eq.) = 4 +1 and Z 2(s) = sr 2C 2 +1 sc 2 sr 2 C 2 +1 sc 2 sr 2 C 2 +1 sτ 2 +1 V in = sr 1 C = 3 sr 1 C = 3 sτ 1 (sτ 3 +1) 4 +1 sc where τ 1 = C 2, τ 2 = R 2 C 2, and τ 3 = 0.25 C 3 The additional pole could also be implemented by a RC network at the output. However, now the output resistance is not small any more. Lecture 090 Filters and Charge Pumps (09/01/03) Page NonIdealities of Active Filters DC Offsets: Model V IO Example v in R 2 vout v in V R IO 1 R 2 v out I OS + I OS + + What is the input and output offset voltages of this example? Output offset voltage = V OS (out) = R V 1 IO + R 2 I OS R 2 Fig Input offset voltage = V OS (in) = V IO + I OS Assume the op amp is a 741 with V IO = 3mV, I OS = 100nA, and = R 2 = 10kΩ. V OS (out) = 3mV + 10kΩ 100nA = 4mV V OS (in) = 3mV + 10kΩ 100nA = 2mV We have seen previously that these input offset voltages can lead to large spurs in the PLL output.

6 Lecture 090 Filters and Charge Pumps (09/01/03) Page NonIdealities of Active Filters Continued Inverting and Noninverting Amplifiers: R 2 vout v IN R 2 vout v IN + Gain and GB = : V in = +R 2 Gain, GB = : (s) V in (s) = R 1 +R 2 Gain, GB : (s) V in (s) = R 1 +R 2 A vd (0) +R A vd(0) +R 2 GB +R 2 s + GB R 1 +R 2 = +R 2 ω H s+ω H V in = R 2 Fig A vd (0) (s) V in (s) = R 2 R 1 +R A vd(0) +R 2 GB (s) V in (s) = R 2 +R 2 s + GB R 1 = R 2 ω H s+ω H +R 2 + Lecture 090 Filters and Charge Pumps (09/01/03) Page NonIdealities of Active Filters Continued Example: Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of +10 and 10. If A vd (0) is 1000, find the actual voltage gains for each amplifier. Solution For the noninverting amplifier, the ratio of R 2 / is 9. A vd (0) /( +R 2 ) = = V in = = rather than 10. For the inverting amplifier, the ratio of R 2 / is 10. A vd (0) +R 2 = = V in = (10) = rather than 10.

7 Lecture 090 Filters and Charge Pumps (09/01/03) Page NonIdealities of Active Filters Continued Finite Gainbandwidth: Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of +1 and 1. If the unitygainbandwidth, GB, of the op amps are 2πMrads/sec, find the upper 3dB frequency for each amplifier. Solution In both cases, the upper 3dB frequency is given by ω H = GB +R 2 For the noninverting amplifier with an ideal gain of +1, the value of R 2 / is zero. ω H = GB = 2π Mrads/sec (1MHz) For the inverting amplifier with an ideal gain of 1, the value of R 2 / is one. ω H = GB = GB 2 = π Mrads/sec (500kHz) Lecture 090 Filters and Charge Pumps (09/01/03) Page NonIdealities of Active Filters Continued Integrators Finite Gain and Gainbandwidth: A vd (s) s C 2 s C where 1 V in = s C 2 A vd (s) = A vd(0)ω a s+ω a = 1 + A vd(s) s C 2 s C 2 +1 = GB GB s+ω a s ω I s A vd (s) (s/ω Ι ) (s/ω Ι ) A vd(s) (s/ω Ι ) (s/ω Ι ) + 1 Case 1: s 0 A vd (s) = A vd (0) V in A vd (0) Case 2: s A vd (s) = GB s Case 3: 0 < s < A vd (s) = (jω)/vin(jω) A vd (0) db 0 db Eq. (1) ω x1 = ω I A vd (0) ω I Eq. (3) Eq. (2) ω x2 = GB log10 ω GB V in V in ω I s Arg[ (jω)/v in (jω)] ω I s s ω I 10A vd (0) 10ωI A vd (0) GB 10 10GB ω I A vd (0) GB log 10 ω

8 Lecture 090 Filters and Charge Pumps (09/01/03) Page CHARGE PUMPS The use of the PFD permits the use of a charge pump in place of the conventional PD and low pass filter. The advantages of the PFD and charge pump include: The capture range is only limited by the VCO output frequency range The static phase error is zero if the mismatches and offsets are negligible. A I 1 B A B PFD I 1 =I 2 =I Q A Q B X Y I 2 C p Q A Q B Fig N t Q A high deposits charge on C p (A leads B). Q B high removes charge from C p (B leads A). Q A and Q B low remains constant. We have seen that a resistor in series with C p is necessary for stability. (QB is high for a short time due to reset delay but the difference between average values between QA and QB still accurately represents the input phase or frequency difference.) Lecture 090 Filters and Charge Pumps (09/01/03) Page Types of Charge Pumps Conventional TriStage Low power consumption, moderate speed, moderate clock skew Low power frequency synthesizers, digital clock generators Current Steering Static current consumption, high speed, moderate clock skew High speed PLL (>100MHz), translation loop, digital clock generators Differential input with SingleEnded output Medium power, moderate speed, low clock skew Lowskew digital clock generators, frequency synthesizers Fully Differential Static current consumption, high speed (>100MHz) Digital clock generators, translation loop, frequency synthesizer (with onchip filter) Advantages of charge pumps Consume less power than active filters Have less noise than active filters Do not have the offset voltage of op amps Provide a pole at the origin More compatible with the objective of putting the filter on chip

9 Lecture 090 Filters and Charge Pumps (09/01/03) Page Nonidealities in Charge Pumps Leakage current: Small currents that flow when the switch is off. Mismatches in the Charge Pump: The up and down (charge and discharge) currents are unequal. Timing Mismatch in PFD: Any mismatch in the time at which the PFD provides the up and down outputs. Charge Sharing: The presence of parasitic capacitors will cause the charge on the desired capacitor to be shared with the parasitic capacitors. Woogeun Rhee, Design of HighPerformance CMOS Charge Pumps in PhaseLocked Loops, Proc. of 1999 ISCAS, Page II545II548, May Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pumps The low pass filter in the PLL can be implemented by: 1.) Active filters which require an op amp 2.) Passive filters and a charge pump. The advantages of a charge pump are: Reduced noise Reduced power consumption No offset voltage Dn Passive Filter Fig V c MP5 MN5 1 I N1 MP3 MP4 2 I N2 MN3 MN4 Dn Dn MP2 MP1 I out MN1 MN2

10 Lecture 090 Filters and Charge Pumps (09/01/03) Page DiscriminatorAided PFD/Charge Pump This circuit reduces the pullin time, T P, and enhances the switching speed of the PLL while maintaining the same noise bandwidth and avoiding modulation damping. Technique: Increase the gain of the phase detector for increasing values of phase error. i P i P θ e θ AD θ AD θ e Characteristic of a Conventional PD Characteristic of a Nonlinear PD Fig The gain of the phase detector is increased when θ e becomes larger than θ AD or smaller than θ AD. During the time the phase detector gain has increased by k, the loop filter bandwidth is also increased by k. CY Yang and SI Liu, FastSwitching Frequency Synthesizer with a DiscriminatorAided Phase Detector, IEEE J. of SolidState Circuits, Vol. 35, No. 10, Oct. 2000, pp Lecture 090 Filters and Charge Pumps (09/01/03) Page DiscriminatorAided Phase Detector (DAPD) Continued Schematic of a phase detector with DAPD and chargepump filter: I p0 (k 2 1)I p0 If the absolute value of the delay between V i and V osc is greater than τ AD, the output signal of the DAPD is high and increases the charge pump current by k 2 and adjusts the loop filter bandwidth. V i V osc Delay τ AD Delay τ AD R U PD V D R U PD V D R U PD V D Low Pass Filter Low Pass U AD Filter DiscriminatorAided Phase Detector 0.35µm CMOS: Switching time for a 448 MHz to 462 MHz step is reduced from 90µs to 15µs (k = 3). I p0 (k 2 1)I p0 D AD R AD FLD C z Fig R z C p V c

11 Lecture 090 Filters and Charge Pumps (09/01/03) Page A TypeI Charge Pump This PLL uses an onchip, passive discretetime loop filter with a single state, chargepump to implement the loop filter. The stabilization zero is created in the discretetime domain rather than using RC time constants. Block diagram of the TypeI, charge pump PLL frequency synthesizer: (Test chip) Sampling pulse generation Clock buffer Vref Two state PFD Vdiv b Charge Pump Vcp Clk Clkb Reset Discretetime domain loop filter Vh RC low pass filter (optional) Programmable divider VCO Vtune Fig B. Zhang, P.E. Allen and J.M. Huard, A Fast Switching PLL Frequency Synthesizer With an OnChip Passive DiscreteTime Loop Filter in 0.25µm CMOS, IEEE J. of SolidState Circuits, vol. 38, no. 6, June 2003, pp Lecture 090 Filters and Charge Pumps (09/01/03) Page TypeI Charge Pump Continued Comparison of a conventional 3state PFD and a 2state PFD: V dd V ref V div D Q Clk Qb Rst Rst Clk Qb D Q NAND Dn V dd V ref V div D Q Clk Qb Rst Rst Clk Qb D Q NAND b Conventional 3state PFD Dual polarity and single polarity charge pumps: 2state PFD Fig I D I D Dn Vcp Vcp I D C load Dual Polarity Single Polarity Fig

12 Lecture 090 Filters and Charge Pumps (09/01/03) Page Single Polarity Charge Pump I Bias M4 M5 M6 M7 R V cp b M8 M9 M12 M10 No matching problems. Fig Lecture 090 Filters and Charge Pumps (09/01/03) Page TypeI Charge Pump Continued The discretetime loop filter: V cp S1 Vch S2 C s Ch Fig12006 F 1 (s) (1z 1 ) k lff 1 (s) s where z = e st s, T s is the sampling period (S1), k lf is a gain constant, and f 1 (s) accounts for the loading effect of the low pass filter. The openloop transfer function of this system is given as, T(s) = (1z 1 ) K dk o k lf f 1 (s) s 2 N T(s) = (st s ) K dk o k lf f 1 (s) s 2 N = T sk d K o k lf f 1 (s) sn which is a Type I system if ω <<2π/T s.

13 Lecture 090 Filters and Charge Pumps (09/01/03) Page TypeI Charge Pump Continued Clock generator and clock waveforms: Discretetime loop filter: 2 Enable 3 V s 4 PRE 5 D O 6 CLK O CLR 1 M4 M8 M17 M18 M19 M23 M20 M24 V cp M35 Reset M28 C s Clk M30 M31 M34 M29 M33 M32 V h C h M6 M7 M25 M26 M27 Clkb M16 M12 M10 M15 M11 M9 Fig Lecture 090 Filters and Charge Pumps (09/01/03) Page TypeI Charge Pump Continued Comparison of the frequency response of the conventional and single state architectures: Conventional architecture Singlestate architecture Results: Conventional Architecture TypeI Architecture Reference spur 53dBc 62dBc Switching time 140µs 30µs Loop filter size Offchip filter Integrated (70pF)

14 Lecture 090 Filters and Charge Pumps (09/01/03) Page Use of Active Filters with Charge Pumps SecondOrder PLL: Dn Vcp Dn C 1 Vcp PLL Crossover Frequency: K 2 τ 2 + K 4 τ K 4 ω c2 = 2 where K = K v NC 1 PLL Settling Time for a Frequency step of ω: 4 t s2 ω K 4 τ 4 c2 2 ln C 1 αn ω 1 τ K where α = Fig θ(t s2 ) θ( ) Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a ThirdOrder Filter The additional pole of a thirdorder PLL provides more spurious suppression. However, the phase lag associated with the pole introduces a stability issue. Dn Circuit: The impedance of the loop filter is, b sτ +1 C 1 Z(s) = b+1 s 2 sτ C 1 where τ = C 1 and b = b+1 +1 C 2 The loop gain for this PLL is LG(s) = K o b sτ +1 2πN b+1 s 2 sτ C 1 b+1 +1 The phase margin of the loop is, τω c3 PM = tan 1 (τω c3 ) tan 1 b+1 where ω c3 is the crossover frequency C 1 Vcp C 2 Dn C 1 + C 2 Vcp Fig

15 Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a ThirdOrder Filter Continued Differentiating with respect to ω c3, shows that max. phase margin occurs when ω c3 = b+1 /τ PM(max) = tan 1 ( b+1 ) tan 1 1 b+1 Maximum phase margin as a function of b = C 1 /C 2. Phase Margin (Degrees) b = C 1 /C 2 Fig Note that for b 1, the phase margin is less than 20. Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a ThirdOrder Filter Continued An analytical expression for settling time is difficult to calculate for the thirdorder filter. The following figure shows the simulated settling time to 10ppm accuracy as a function of phase margin when ω/n = 0.04 (ω i = ω ref ). t s3 /T i = ts3/t ref Phase Margin Degrees For ω/n < 0.04 and 20 <PM<79, we may estimate the settling time to 10ppm accuracy as t s3 2π ω c3 [ PM PM ]

16 Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a ThirdOrder Filter Continued A loop filter design recipe: 1.) Find K v for the VCO. 2.) Choose a desired PM and find b from the max. PM equation. 3.) Choose the crossover frequency, ω c3, and find τ from ω c3 = b+1 /τ. 4.) Select C 1 and such that they satisfy K v b 2πN b+1 = C 1 τ 2 b+1 5.) Calculate the noise contribution of R 2 1. If the calculated noise is negligible the design is complete. If not, then go back to step 4.) and increase C 1. Example: Let K v = 10 7 rads/sec., N = 1000, PM = 50 and f c3 = 10kHz. Now, 50 = tan 1 ( b+1 ) tan 1 1 b 6.65 (by iteration) b+1 b+1 τ = 2π f c3 = π 1000 = 0.44 msec If = 200µA, then C 1 = K v b τ 2 2πN b+1 b+1 = nf = τ C 1 = 22.72kΩ Noise = 4kTR = 4(1.38x10 23 )(300)(22.72kΩ) = 3.76x10 16 V 2 /Hz Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter To further reduce the spurs with out decreasing the crossover frequency and thereby increasing the settling time, an additional pole needs to be added to the loop. Circuit: C 2 Dn C 1 R 3 C 2 Vcp C 3 Dn C 1 + R 3 Vcp C 3 The impedance of the passive filter is given as, sτ + 1 Z(s) = sc 1 1+ C 2 C + C 3 1 C 1 B(sτ) 2 + Asτ + 1 where Fig b τ 2 τ 1+ C 2 C 1 A = 1+b, B = b τ 2C 2 C 1 1+b τc 1, τ = C 1, τ 3 = R 3 C 3 and b = C 2 +C 3

17 Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter Continued Phase margin: PM = tan 1 (τω c4 ) tan 1 A(τω c4 ) 1B(τω c4 ) 2 where ω c4 = crossover frequency The maximum phase margin is obtained when the derivative of the above equation with respect to ω c4 is set to zero. The results are: ω c4 = 1 1 τ 2 2B+AB+AA 2 2B+AB+AA 2 2 4(1A) B(BA) + B(BA) B(BA) For ω c4 to be the crossover frequency, it must satisfy the following equation, K v 1+(τω c4 ) 2 1+b 2πN (Aτω c4 ) 2 +[1B(τω c4 ) 2 ] 2 = C 1 b ω c4 2 Practical simplifications: A positive phase margin Zero lower than the two high frequency poles C 2 C < 1 1 For the fourth pole not to decrease the phase margin it has to be more than a decade away from the zero, therefore, b τ 2 τ << 1. With these conditions we find that B << A. Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter Continued If B << A, then the previous relationships become, A 1 1+b, ω 1 c4 τ A 1+b τ and K v b 2πN 1+b C 1 τ 2 1+b The maximum phase margin also simplifies to, PM(max) tan 1 ( 1+b) tan b Exact phase margin:

18 Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter Continued Simulation is used to estimate the settling time of the fourthorder loop to 10 ppm accuracy when ω/n < 0.04: t 4 /T i = t s4 /T ref Phase Margin Degrees Note that the settling time at a given phase margin is independent of τ 2 /τ and is the same as that of a thirdorder loop. Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter Continued Spur suppression of the fourthorder filter.

19 Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter Continued Loop filter design procedure: 1.) Find K v for the VCO. 2.) Choose a desired phase margin and find b. (If PM = 50, then b = 6.5) 3.) Choose the crossover frequency ω c4 and find τ. (τ 2.7/ω c4 if b = 6.5) 4.) Choose the desired spur attenuation and find τ 2 /τ from the previous page. 5.) Select C 1 and such that they satisfy K v b 2πN 1+b C 1 τ 2 1+b. 6.) Calculate the noise contribution of and R 3. Example: Let K v = 10 7 rads/sec., N = 1000, PM = 50, f c4 = 1kHz and f ref = 100kHz. Since PM = 50, b = 6.5 τ 2.7/ω c4 = 2.7/(2π 1000) = 430µsec. Let us choose τ 2 /τ as 0.1 which corresponds to about 90dB of suppression. If = 200µA, then C 1 = K v b τ 2 2πN b+1 b+1 = nf = τ C 1 = 23.09kΩ τ 2 = 0.1τ = 43µsec If C 3 = 1nF, then R 3 = τ 2 /C 3 = 43µsec/1nF = 43kΩ Noise: v 2 R1 = 4kT = x10 16 V 2 /Hz and v 2 R3 = 4kTR 3 = 7.12 x10 16 V 2 /Hz Lecture 090 Filters and Charge Pumps (09/01/03) Page Charge Pump with a FourthOrder Filter Continued Open loop transfer function for a typical fourthorder PLL: PSPICE File: Fourthorder, chargepump PLL loop gain.param N=1000, KVCO=1E7, T=0.43E3, T2=43E6, KD=1, E=10.PARAM A= B= *VCO Noise Transfer Function VIN 1 0 AC 1.0 RIN K EDPLL1 2 0 LAPLACE {V(1)}= +{KD*KVCO*46.52E6*(S*T+1)/(S+E)/(S+E)/(B*T*T*S*S+A*T*S+1)} RDPLL K *Steady state AC analysis.ac DEC MEG.PRINT AC VDB(2) VP(2).PROBE.END db or Degrees Magnitude Phase Margin 90 Phase Shift Frequency (Hz) Fig

20 Lecture 090 Filters and Charge Pumps (09/01/03) Page SUMMARY Filters Determines the dynamic performance of the PLL Active and passive filters Order of the filter higher the order, the more noise and spur suppression Nonidealities of active filters DC offsets Finite op amp gain Finite gainbandwidth Noise Charge Pumps Avoid the use of the op amp to achieve a pole at the origin (TypeII systems) Nonidealities in charge pumps Leakage current Mismatches in the up and down currents Timing mismatches Charge sharing

Lecture 120 Filters and Charge Pumps (6/9/03) Page 120-1

Lecture 120 Filters and Charge Pumps (6/9/03) Page 120-1 Lecture 120 Filters and Charge Pumps (6/9/03) Page 1201 LECTURE 120 FILTERS AND CHARGE PUMPS (READING: [4,6,9,10]) Objective The objective of this presentation is examine the circuits aspects of loop filters

More information

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

More information

Behavior of Phase-Locked Loops

Behavior of Phase-Locked Loops Phase-Locked Loops Behavior of Phase-Locked Loops Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering Mathematical Model of VCOs 6- Phase of Signals V0 = Vmsin 0t V = Vmsin

More information

Introduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D.

Introduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D. Introduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Presentation Outline What is Phase Locked Loop (PLL) Basic PLL System Problem of Lock Acquisition Phase/Frequency

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL

24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL 24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL John G. Maneatis 1, Jaeha Kim 1, Iain McClatchie 1, Jay Maxey 2, Manjusha Shankaradas 2 True Circuits, Los Altos,

More information

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 = ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.

More information

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

More information

Homework Assignment 11

Homework Assignment 11 Homework Assignment Question State and then explain in 2 3 sentences, the advantage of switched capacitor filters compared to continuous-time active filters. (3 points) Continuous time filters use resistors

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1 Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators

More information

Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. University of California at San Diego, La Jolla, CA

Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. University of California at San Diego, La Jolla, CA Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL Kevin Wang 1, Ashok Swaminathan 1,2, Ian Galton 1 1 University of California at San Diego, La Jolla, CA 2 NextWave

More information

D/A Converters. D/A Examples

D/A Converters. D/A Examples D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

Fundamentals of PLLs (III)

Fundamentals of PLLs (III) Phase-Locked Loops Fundamentals of PLLs (III) Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering Phase transfer function in linear model i (s) Kd e (s) Open-loop transfer

More information

Lecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters

Lecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters Lecture 6, ATIK Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters What did we do last time? Switched capacitor circuits The basics Charge-redistribution analysis Nonidealties

More information

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5. Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232-242 Two-stage op-amp Analysis Strategy Recognize

More information

Feedback design for the Buck Converter

Feedback design for the Buck Converter Feedback design for the Buck Converter Portland State University Department of Electrical and Computer Engineering Portland, Oregon, USA December 30, 2009 Abstract In this paper we explore two compensation

More information

ELECTRONIC SYSTEMS. Basic operational amplifier circuits. Electronic Systems - C3 13/05/ DDC Storey 1

ELECTRONIC SYSTEMS. Basic operational amplifier circuits. Electronic Systems - C3 13/05/ DDC Storey 1 Electronic Systems C3 3/05/2009 Politecnico di Torino ICT school Lesson C3 ELECTONIC SYSTEMS C OPEATIONAL AMPLIFIES C.3 Op Amp circuits» Application examples» Analysis of amplifier circuits» Single and

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

Lecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1

Lecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1 Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs

More information

System on a Chip. Prof. Dr. Michael Kraft

System on a Chip. Prof. Dr. Michael Kraft System on a Chip Prof. Dr. Michael Kraft Lecture 3: Sample and Hold Circuits Switched Capacitor Circuits Circuits and Systems Sampling Signal Processing Sample and Hold Analogue Circuits Switched Capacitor

More information

ELEN 610 Data Converters

ELEN 610 Data Converters Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power

More information

Today. 1/25/11 Physics 262 Lecture 2 Filters. Active Components and Filters. Homework. Lab 2 this week

Today. 1/25/11 Physics 262 Lecture 2 Filters. Active Components and Filters. Homework. Lab 2 this week /5/ Physics 6 Lecture Filters Today Basics: Analog versus Digital; Passive versus Active Basic concepts and types of filters Passband, Stopband, Cut-off, Slope, Knee, Decibels, and Bode plots Active Components

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

L4970A 10A SWITCHING REGULATOR

L4970A 10A SWITCHING REGULATOR L4970A 10A SWITCHING REGULATOR 10A OUTPUT CURRENT.1 TO 40 OUTPUT OLTAGE RANGE 0 TO 90 DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULA- TION INTERNAL CURRENT LIMITING PRECISE.1 ± 2 ON CHIP REFERENCE

More information

SC70, 1.6V, Nanopower, Beyond-the-Rails Comparators With/Without Reference

SC70, 1.6V, Nanopower, Beyond-the-Rails Comparators With/Without Reference 19-1862; Rev 4; 1/7 SC7, 1.6V, Nanopower, Beyond-the-Rails General Description The nanopower comparators in space-saving SC7 packages feature Beyond-the- Rails inputs and are guaranteed to operate down

More information

Discrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2)

Discrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2) Discrete Time Signals and Switched Capacitor Circuits (rest of chapter 9 + 0., 0.2) Tuesday 6th of February, 200, 9:5 :45 Snorre Aunet, sa@ifi.uio.no Nanoelectronics Group, Dept. of Informatics Office

More information

Design of CMOS Adaptive-Bandwidth PLL/DLLs

Design of CMOS Adaptive-Bandwidth PLL/DLLs Design of CMOS Adaptive-Bandwidth PLL/DLLs Jaeha Kim May 2004 At Samsung Electronics, Inc. Adaptive-Bandwidth PLL/DLL PLL/DLLs that scale their loop dynamics proportionally with the reference frequency

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Charge-Pump Phase-Locked Loops

Charge-Pump Phase-Locked Loops Phase-Locked Loos Charge-Pum Phase-Locked Loos Ching-Yuan Yang National Chung-Hsing University Deartment of Electrical Engineering Concetual oeration of a hase-frequency detector (PFD) PFD 5- Ching-Yuan

More information

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH ) Lecture 30 Compensation of Op AmpsII (/26/04) Page 30 LECTURE 30 COMPENSATION OF OP AMPSII (READING: GHLM 638652, AH 260269) INTRODUCTION The objective of this presentation is to continue the ideas of

More information

Discrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2)

Discrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2) Discrete Time Signals and Switched Capacitor Circuits (rest of chapter 9 + 10.1, 10.2) Tuesday 16th of February, 2010, 0, 9:15 11:45 Snorre Aunet, sa@ifi.uio.no Nanoelectronics Group, Dept. of Informatics

More information

H(s) = 2(s+10)(s+100) (s+1)(s+1000)

H(s) = 2(s+10)(s+100) (s+1)(s+1000) Problem 1 Consider the following transfer function H(s) = 2(s10)(s100) (s1)(s1000) (a) Draw the asymptotic magnitude Bode plot for H(s). Solution: The transfer function is not in standard form to sketch

More information

Figure Circuit for Question 1. Figure Circuit for Question 2

Figure Circuit for Question 1. Figure Circuit for Question 2 Exercises 10.7 Exercises Multiple Choice 1. For the circuit of Figure 10.44 the time constant is A. 0.5 ms 71.43 µs 2, 000 s D. 0.2 ms 4 Ω 2 Ω 12 Ω 1 mh 12u 0 () t V Figure 10.44. Circuit for Question

More information

Input and Output Impedances with Feedback

Input and Output Impedances with Feedback EE 3 Lecture Basic Feedback Configurations Generalized Feedback Schemes Integrators Differentiators First-order active filters Second-order active filters Review from Last Time Input and Output Impedances

More information

6.2 INTRODUCTION TO OP AMPS

6.2 INTRODUCTION TO OP AMPS Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis

More information

Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

More information

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

More information

Lecture 21: Packaging, Power, & Clock

Lecture 21: Packaging, Power, & Clock Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or

More information

UNIVERSITÀ DEGLI STUDI DI CATANIA. Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo

UNIVERSITÀ DEGLI STUDI DI CATANIA. Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo UNIVERSITÀ DEGLI STUDI DI CATANIA DIPARTIMENTO DI INGEGNERIA ELETTRICA, ELETTRONICA E DEI SISTEMI Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo

More information

ECE 6412, Spring Final Exam Page 1

ECE 6412, Spring Final Exam Page 1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

More information

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2

More information

A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load

A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1 Outline

More information

Modeling All-MOS Log-Domain Σ A/D Converters

Modeling All-MOS Log-Domain Σ A/D Converters DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 1/22 Modeling All-MOS Log-Domain Σ A/D Converters X.Redondo 1, J.Pallarès 2 and F.Serra-Graells 1 1 Institut de Microelectrònica

More information

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM 425434 and 624638, AH 249260) INTRODUCTION The objective of this presentation is to present the

More information

Nonlinear Behavior Modeling of Charge-Pump Based Frequency Synthesizers

Nonlinear Behavior Modeling of Charge-Pump Based Frequency Synthesizers 2005 WSEAS Int. Conf. on DYNAMICAL SYSTEMS and CONTROL, Venice, Italy, November 2-4, 2005 (pp325-329) Nonlinear Behavior Modeling of Charge-Pump Based Frequency Synthesizers TORD JOHNSON Department of

More information

The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A =

The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A = The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A = 10 10 4. Section Break Difficulty: Easy Learning Objective: Understand how real operational

More information

Quick Review. ESE319 Introduction to Microelectronics. and Q1 = Q2, what is the value of V O-dm. If R C1 = R C2. s.t. R C1. Let Q1 = Q2 and R C1

Quick Review. ESE319 Introduction to Microelectronics. and Q1 = Q2, what is the value of V O-dm. If R C1 = R C2. s.t. R C1. Let Q1 = Q2 and R C1 Quick Review If R C1 = R C2 and Q1 = Q2, what is the value of V O-dm? Let Q1 = Q2 and R C1 R C2 s.t. R C1 > R C2, express R C1 & R C2 in terms R C and ΔR C. If V O-dm is the differential output offset

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specificatio The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

LECTURE 3 CMOS PHASE LOCKED LOOPS

LECTURE 3 CMOS PHASE LOCKED LOOPS Lecture 03 (8/9/18) Page 3-1 LECTURE 3 CMOS PHASE LOCKED LOOPS Topics The acquisition process unlocked state Noise in linear PLLs Organization: Systems Perspective Types of PLLs and PLL Measurements PLL

More information

ECEN 610 Mixed-Signal Interfaces

ECEN 610 Mixed-Signal Interfaces ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 140 Simple Op Amps (2/11/02) Page 140-1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

More information

Operational Amplifiers

Operational Amplifiers Operational Amplifiers A Linear IC circuit Operational Amplifier (op-amp) An op-amp is a high-gain amplifier that has high input impedance and low output impedance. An ideal op-amp has infinite gain and

More information

ESE319 Introduction to Microelectronics. Feedback Basics

ESE319 Introduction to Microelectronics. Feedback Basics Feedback Basics Feedback concept Feedback in emitter follower Stability One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability

More information

An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor. ΔΣ Modulator. Electronic Design Automation Laboratory

An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor. ΔΣ Modulator. Electronic Design Automation Laboratory Electronic Design Automation Laboratory National Central University Department of Electrical Engineering, Taiwan ( R.O.C) An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor

More information

ENGN3227 Analogue Electronics. Problem Sets V1.0. Dr. Salman Durrani

ENGN3227 Analogue Electronics. Problem Sets V1.0. Dr. Salman Durrani ENGN3227 Analogue Electronics Problem Sets V1.0 Dr. Salman Durrani November 2006 Copyright c 2006 by Salman Durrani. Problem Set List 1. Op-amp Circuits 2. Differential Amplifiers 3. Comparator Circuits

More information

SGM nA, Single Rail-to-Rail I/O Operational Amplifier

SGM nA, Single Rail-to-Rail I/O Operational Amplifier GENERAL DESCRIPTION The SGM8041 is guaranteed to operate with a single supply voltage as low as 1.4V, while drawing less than 710nA (TYP) of quiescent current. This device is also designed to support rail-to-rail

More information

Electronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory

Electronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory Electronic Circuits Prof. Dr. Qiuting Huang 6. Transimpedance Amplifiers, Voltage Regulators, Logarithmic Amplifiers, Anti-Logarithmic Amplifiers Transimpedance Amplifiers Sensing an input current ii in

More information

2 nd Order PLL Design and Analysis

2 nd Order PLL Design and Analysis nd Order PLL Design and Analysis S REF Phase Detector Σ K f Loop Filter VCO K V s R C Loop Divider Fig. : nd Order PLL with Current-Mode Phase Detector useful functions and identities Units Constants Table

More information

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

More information

GMU, ECE 680 Physical VLSI Design 1

GMU, ECE 680 Physical VLSI Design 1 ECE680: Physical VLSI Design Chapter VII Timing Issues in Digital Circuits (chapter 10 in textbook) GMU, ECE 680 Physical VLSI Design 1 Synchronous Timing (Fig. 10 1) CLK In R Combinational 1 R Logic 2

More information

Nyquist-Rate A/D Converters

Nyquist-Rate A/D Converters IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling

More information

EE247 Analog-Digital Interface Integrated Circuits

EE247 Analog-Digital Interface Integrated Circuits EE247 Analog-Digital Interface Integrated Circuits Fall 200 Name: Zhaoyi Kang SID: 22074 ******************************************************************************* EE247 Analog-Digital Interface Integrated

More information

ECEN 607 (ESS) Op-Amps Stability and Frequency Compensation Techniques. Analog & Mixed-Signal Center Texas A&M University

ECEN 607 (ESS) Op-Amps Stability and Frequency Compensation Techniques. Analog & Mixed-Signal Center Texas A&M University ECEN 67 (ESS) Op-Amps Stability and Frequency Compensation Techniques Analog & Mixed-Signal Center Texas A&M University Stability of Linear Systems Harold S. Black, 97 Negative feedback concept Negative

More information

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm-1 Exam (Solution)

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm-1 Exam (Solution) Georgia Institute of Technology School of Electrical and Computer Engineering Midterm-1 Exam (Solution) ECE-6414 Spring 2012 Friday, Feb. 17, 2012 Duration: 50min First name Solutions Last name Solutions

More information

ECE3050 Assignment 7

ECE3050 Assignment 7 ECE3050 Assignment 7. Sketch and label the Bode magnitude and phase plots for the transfer functions given. Use loglog scales for the magnitude plots and linear-log scales for the phase plots. On the magnitude

More information

Refinements to Incremental Transistor Model

Refinements to Incremental Transistor Model Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes

More information

Stability and Frequency Compensation

Stability and Frequency Compensation 類比電路設計 (3349) - 2004 Stability and Frequency ompensation hing-yuan Yang National hung-hsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,

More information

ENGR-4300 Spring 2009 Test 2. Name: SOLUTION. Section: 1(MR 8:00) 2(TF 2:00) 3(MR 6:00) (circle one) Question I (20 points): Question II (20 points):

ENGR-4300 Spring 2009 Test 2. Name: SOLUTION. Section: 1(MR 8:00) 2(TF 2:00) 3(MR 6:00) (circle one) Question I (20 points): Question II (20 points): ENGR43 Test 2 Spring 29 ENGR43 Spring 29 Test 2 Name: SOLUTION Section: 1(MR 8:) 2(TF 2:) 3(MR 6:) (circle one) Question I (2 points): Question II (2 points): Question III (17 points): Question IV (2 points):

More information

D is the voltage difference = (V + - V - ).

D is the voltage difference = (V + - V - ). 1 Operational amplifier is one of the most common electronic building blocks used by engineers. It has two input terminals: V + and V -, and one output terminal Y. It provides a gain A, which is usually

More information

Design of Analog Integrated Circuits

Design of Analog Integrated Circuits Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

More information

ANALYSIS OF SMALL-SIGNAL MODEL OF A PWM DC-DC BUCK-BOOST CONVERTER IN CCM.

ANALYSIS OF SMALL-SIGNAL MODEL OF A PWM DC-DC BUCK-BOOST CONVERTER IN CCM. ANALYSIS OF SMALL-SIGNAL MODEL OF A PWM DC-DC BUCK-BOOST CONVERTER IN CCM. A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering By Julie J. Lee

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

Problem Set 4 Solutions

Problem Set 4 Solutions University of California, Berkeley Spring 212 EE 42/1 Prof. A. Niknejad Problem Set 4 Solutions Please note that these are merely suggested solutions. Many of these problems can be approached in different

More information

Sample-and-Holds David Johns and Ken Martin University of Toronto

Sample-and-Holds David Johns and Ken Martin University of Toronto Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters

More information

Chapter 9: Controller design

Chapter 9: Controller design Chapter 9. Controller Design 9.1. Introduction 9.2. Effect of negative feedback on the network transfer functions 9.2.1. Feedback reduces the transfer function from disturbances to the output 9.2.2. Feedback

More information

EE 508 Lecture 4. Filter Concepts/Terminology Basic Properties of Electrical Circuits

EE 508 Lecture 4. Filter Concepts/Terminology Basic Properties of Electrical Circuits EE 58 Lecture 4 Filter Concepts/Terminology Basic Properties of Electrical Circuits Review from Last Time Filter Design Process Establish Specifications - possibly T D (s) or H D (z) - magnitude and phase

More information

Pipelined multi step A/D converters

Pipelined multi step A/D converters Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 04 Nov 2006 Motivation for multi step A/D conversion Flash converters: Area and power consumption increase

More information

A 51pW Reference-Free Capacitive-Discharging Oscillator Architecture Operating at 2.8Hz. Sept Hui Wang and Patrick P.

A 51pW Reference-Free Capacitive-Discharging Oscillator Architecture Operating at 2.8Hz. Sept Hui Wang and Patrick P. A 51pW Reference-Free apacitive-discharging Oscillator Architecture Operating at 2.8Hz Sept. 28 2015 Hui Wang and Patrick P. Mercier Wireless Sensing Platform Long-Term Health Monitoring - Blood glucose

More information

Electronics and Communication Exercise 1

Electronics and Communication Exercise 1 Electronics and Communication Exercise 1 1. For matrices of same dimension M, N and scalar c, which one of these properties DOES NOT ALWAYS hold? (A) (M T ) T = M (C) (M + N) T = M T + N T (B) (cm)+ =

More information

EE247 Lecture 16. Serial Charge Redistribution DAC

EE247 Lecture 16. Serial Charge Redistribution DAC EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic

More information

Lecture 10, ATIK. Data converters 3

Lecture 10, ATIK. Data converters 3 Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering

More information

Q. 1 Q. 25 carry one mark each.

Q. 1 Q. 25 carry one mark each. GATE 5 SET- ELECTRONICS AND COMMUNICATION ENGINEERING - EC Q. Q. 5 carry one mark each. Q. The bilateral Laplace transform of a function is if a t b f() t = otherwise (A) a b s (B) s e ( a b) s (C) e as

More information

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs Advanced Analog Integrated Circuits Operational Transconductance Amplifier II Multi-Stage Designs Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard

More information

EE100Su08 Lecture #9 (July 16 th 2008)

EE100Su08 Lecture #9 (July 16 th 2008) EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart

More information

u (t t ) + e ζωn (t tw )

u (t t ) + e ζωn (t tw ) LINEAR CIRCUITS LABORATORY OSCILLATIONS AND DAMPING EFFECT PART I TRANSIENT RESPONSE TO A SQUARE PULSE Transfer Function F(S) = ω n 2 S 2 + 2ζω n S + ω n 2 F(S) = S 2 + 3 RC ( RC) 2 S + 1 RC ( ) 2 where

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI

An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI Dennis Fischette, Richard DeSantis, John H. Lee 1 AMD, Sunnyvale, California, USA 1 MIT, Cambridge, Massachusetts,

More information

Maxim Integrated Products 1

Maxim Integrated Products 1 19-4187; Rev 4; 7/1 μ μ PART AMPS PER PACKAGE PIN- PACKAGE + * TOP MARK MAX965AZK+ 1 5 SOT3 ADSI MAX965AZK/V+ 1 5 SOT3 ADSK MAX965AUA+ 1 8 μmax-ep* AABI MAX965ATA+ 1 8 TDFN-EP* BKX MAX9651AUA+ 8 μmax-ep*

More information

Boost Charge Pump Current PLL

Boost Charge Pump Current PLL oost Charge Pump Current PLL ormal Charge Pump f R Σ K φ oost K v oost R f O K φb oost Charge Pump C C Fig. : 3 rd -Order PLL with Current-Mode Phase-Detector and oosted Charge Pump useful functions and

More information

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors Piet Vanassche, Georges Gielen and Willy Sansen Katholieke Universiteit Leuven - ESAT/MICAS

More information

SGM nA, Dual Rail-to-Rail I/O Operational Amplifier

SGM nA, Dual Rail-to-Rail I/O Operational Amplifier SGM842 67nA, Dual Rail-to-Rail I/O GENERAL DESCRIPTION The SGM842 is guaranteed to operate with a single supply voltage as low as 1.4V, while drawing less than 67nA (TYP) of quiescent current per amplifier.

More information

Successive Approximation ADCs

Successive Approximation ADCs Department of Electrical and Computer Engineering Successive Approximation ADCs Vishal Saxena Vishal Saxena -1- Successive Approximation ADC Vishal Saxena -2- Data Converter Architectures Resolution [Bits]

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

SWITCHED CAPACITOR AMPLIFIERS

SWITCHED CAPACITOR AMPLIFIERS SWITCHED CAPACITOR AMPLIFIERS AO 0V 4. AO 0V 4.2 i Q AO 0V 4.3 Q AO 0V 4.4 Q i AO 0V 4.5 AO 0V 4.6 i Q AO 0V 4.7 Q AO 0V 4.8 i Q AO 0V 4.9 Simple amplifier First approach: A 0 = infinite. C : V C = V s

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information