An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI

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1 An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI Dennis Fischette, Richard DeSantis, John H. Lee 1 AMD, Sunnyvale, California, USA 1 MIT, Cambridge, Massachusetts, USA Custom Integrated Circuits Conference September 16,

2 Outline Motivation Loop Measurement Circuit Algorithm Architecture Silicon Results Conclusion 2

3 PLL Closed-Loop Transfer Function Frequency domain model Input: excess phase modulation of input (reference) clock Output: excess phase modulation of feedback clock feedback () t = 2π f t φ ( t ) φ + refclk PLL () t = 2π f t f ( φ ( t )) φ + c c mod mod Normalized Jitter Transfer (db) kHz Peaking BW 1MHz Low damping High damping 10MHz Jitter Modulation Frequency 100MHz 3

4 Motivation Strict bandwidth and peaking requirements e.g., PCI Express Generation 5 Gb/s 5 88 MHz BW / < 1 db peaking 8 16 MHz BW / < 3 db peaking Locktime (function of BW) ) increasingly important given frequent exit from sleep/power-save save states Device PVT variation simulations inadequate Standard methods Spectrum Analyzer, Waveform Generator Problems with standard methods Slow expensive Wafer? Package? Product? inflexible 4

5 Outline Motivation Loop Measurement Circuit Algorithm Architecture Silicon Results Conclusion 5

6 Simulated Step Response vs. Time MaxOvershoot Phase Error (ns) T crossover Time (µs)( 6

7 Basis of Algorithm Relationship between time & frequency domain behavior Lower BW higher T crossover Larger input phase step larger peaking Linear Fit Linear Fit T crossover (µs) T refclk Phase Step 50% 75% MaxOvershoot (ns) T refclk Phase Step 50% 75% /BW (µs) Peaking (db) 7

8 Closed-Form Equations for Phase Error Damping Factor ζ < 1 (underdamped) φ err () t = φ step e cos ωnt 2 ς 1 ς sin ωnt 1 ς 2 1 ς ςω t 2 n Damping Factor ζ = 1 (critically damped) φ err ωnt () t = φ e ( 1 ω t ) step n Damping Factor ζ > 1 (overdamped) φ err () t = φ step e ςω t n cosh ωnt ς 2 1 ς ς 2 1 sinh ωnt ς 2 1 Source: Gardner, Phaselock Techniques,,

9 Closed-Form Equations vs. Simulations % T refclk Phase Step 75% T refclk Phase Step 5 T crossover (µs) Simulation Equation MaxOvershoot (ns) Simulation Equation /BW (µs) Peaking (db) Equations become less accurate at high ζ due to smoothing loop filter pole for reference spur reduction 9

10 PLL + Loop Measurement Circuit Digital State Machine no analog circuits Minimal overhead/intrusion communicates with feedback divider only Instantaneously steps feedback clock phase programmable, directional Measures T crossover and MaxOvershoot 10

11 Loop Measurement Circuit Control Unit RefClk Start From JTAG D Q D Q D Q D Q RefRise N[5:0]+K[5:0] Edge Detector RefFall StartRise Edge Detector N[5:0] FbRise BwValid RefRise En Clr En Hold D Delay D D until until En=1 Q D Q En=1 Hold D StepEn until Clr=1 FbDiv[5:0] To Feedback Divider T crossover Detector FbClk RefClk D Q BBPD En D Q Load_BBPD BBPD1 En D Q BBPD2 RefRise BwEn En BW Q Counter BwCnt[9:0] To JTAG BwValid MaxOvershoot Detector FbCnt[5:0] From Feedback Divider RefRise En D Q Compare NewMaxOS SmplCnt[5:0] UpdateOS D Q RefFall MaxOvershoot[5:0] To JTAG 11

12 Control Unit RefClk RefRise RefFall Start StartRise FbRise StepEn BwEn RefClk Start From JTAG D Q D Q D Q D Q RefRise N[5:0]+K[5:0] Edge Detector RefFall StartRise Edge Detector N[5:0] FbRise BwValid RefRise En Clr En Hold D Delay D D until until En=1 Q D Q En=1 Hold D StepEn until Clr=1 BwEn FbDiv[5:0] To Feedback Divider To T crossover Detector 12

13 Control Unit and Phase Step RefClk StepEn FbDiv[5:0] FbCnt[5:0] FbClk BwEn BwCnt[9:0] RefClk Start From JTAG D Q D Q D Q D Q RefRise N[5:0]+K[5:0] Edge Detector RefFall StartRise Edge Detector N[5:0] FbRise BwValid RefRise En Clr En Hold D Delay D D until until En=1 Q D Q En=1 Hold D StepEn until Clr=1 BwEn FbDiv[5:0] To Feedback Divider To T crossover Detector 13

14 Bandwidth/Tcrossover Test RefClk FbClk BBPD Load_BBPD BBPD1 BBPD2 BwValid BwCnt[5:0]

15 Peaking/MaxOvershoot Test 15

16 Outline Motivation Loop Measurement Circuit Algorithm Architecture Silicon Results Conclusion 16

17 Simulations vs. Measurements 100 MHz refclk, feedback divisor = 50 (2x25) Case R lpf (kω) I cp (µa) Simulated Bandwidth (MHz) Part 1 Measured Part 2 Part 3 Simulated Peaking (db) Part 1 Measured Part 2 Part 3 17

18 Measured T crossover vs. 1/BW T crossover (µs) T refclk Phase Step 50% measured 75% simulated 75% measured /BW (µs) 18

19 Measured MaxOvershoot vs. Peaking 3.0 MaxOvershoot (ns) T refclk Peaking (db) refclk Phase Step 50% simulated 50% measured 75% simulated 75% measured 19

20 Power and Area Power (simulated) = 2.5 mw Output frequency = 2.5 GHz VDD = 1.2 V Clocks gated when not in use Area = 2,750 µm 2 45-nm SOI-CMOS Can easily be reduced by 40 50% by replacing non-critical sense-amplifier flip-flops with smaller master-slave flip-flops and optimizing overshoot comparator Layout area not a serious concern in this design 20

21 Outline Motivation Loop Measurement Circuit Algorithm Architecture Silicon Results Conclusions 21

22 Conclusion An on-chip, all-digital state machine can be used to accurately estimate PLL bandwidth and peaking with potentially large savings in tester time. This flexible circuit may be used from wafer level to product level, minimizing die/package waste and allowing for adaptive PLL loop calibration. 22

23 Acknowledgments Alvin Loke - AMD Gerry Talbot - AMD 23

An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI

An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI An On-Chip All-Digial Measuremen Circui o Characerize Phase-Locked Loop Response in 45-nm SOI Dennis Fischee, Richard DeSanis, John H. Lee AMD, Sunnyvale, California, USA MIT, Cambridge, Massachuses, USA