74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
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1 INTEGRATED CIRCUITS inputs/outputs; positive-edge trigger (3-State) 1998 Sep 24
2 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7V to 3.6V Complies with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TT levels 9-bit positive edge-triggered register Independent register and 3-State buffer operation Flow-through pin-out architecture DESCRIPTION The is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TT families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The is a 9-bit D-type flip-flop with common clock (CP), Clock Enable (CE), Master Reset (MR) and 3-State outputs for bus-oriented applications. The nine flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the OW-to-IG CP transition provided CE is OW. When CE is IG the flip-flops hold their data. A OW on MR resets all flip-flops. When OE is OW, the contents of the nine flip-flops is available at the outputs. When OE is IG, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA = 0 V; T amb = 25 C; t r = t f 2.5 ns SYMBO PARAMETER CONDITIONS TYPICA UNIT Propagation delay 5.1 ns CP to Q n C = 50 pf; t P /t P Propagation delay = 3.3 V 5.2 ns MR to Q n C f max Maximum clock frequency = 50 pf; 150 Mz = 3.3 V C I Input capacitance 5.0 pf Power dissipation capacitance per C PD Notes 1 and 2 27 pf flip-flop NOTES: 1. C PD is used to determine the dynamic power dissipation (P D in µw) P D = C PD V 2 CC f i (C V 2 CC f o ) where: f i = input frequency in Mz; C = output load capacity in pf; f o = output frequency in Mz; = supply voltage in V; (C V 2 CC f o ) = sum of the outputs. 2. The condition is V I = to ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDERING CODE PKG. DWG. # 24-Pin Plastic SO 40 C to +85 C D SOT Pin Plastic SSOP Type II 40 C to +85 C DB SOT Pin Plastic TSSOP Type I 40 C to +85 C PW SOT Sep
3 PIN DESCRIPTION PIN NUMBER SYMBO NAME AND FUNCTION 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10 D 0 to D 8 Output enable input (active OW) Data inputs 11 MR Master reset (active OW) 12 Ground (0 V) 13 CP Clock pulse (active rising) 14 CE Clock enable (active OW) 23, 22, 21, 20, 19, 18, 17, 16, 15 Q 0 to Q 8 3-State flip-flop outputs 24 Positive supply voltage FUNCTION TABE OPERATING MODES INPUTS OE MR CE CP D n INTERNA FIP-FOPSFOPS OUTPUTS Clear X X X Q 0 to Q 8 oad and read register l h oad register and disable outputs X X l h Z Z old NC X NC NC = IG voltage level h = IG voltage level one set-up time prior to the OW-to-IG CP transition = OW voltage level l = OW voltage level one set-up time prior to the OW-to-IG CP transition Z = high impedance OFF-state = OW to IG clock transition NC= no change PIN CONFIGURATION OGIC SYMBO 11 1 OE 1 24 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 MR Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 CE 2 MR OE D 0 Q 0 3 D 1 Q 1 4 D 2 Q 2 5 D 3 Q 3 6 D 4 Q 4 7 D 5 Q 5 8 D 6 Q 6 9 D 7 Q 7 10 D 8 Q 8 CP CE CP SA SA Sep 24 3
4 OGIC SYMBO (IEEE/IEC) FUNCTIONA DIAGRAM EN R G1 1C D 0 D 1 D 2 D 3 Q 0 Q 1 Q 2 Q D D 4 D 5 FF0 to FF8 3 STATE OUTPUTS Q 4 Q D 6 Q D 7 Q D 8 Q CP CE MR OE SA00420 SA00421 OGIC DIAGRAM D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 MR D R Q CE CP CP CP CP CP CP CP CP CP FF0 FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 SA Sep 24 4
5 RECOMMENDED OPERATING CONDITIONS IMITS SYMBO PARAMETER CONDITIONS MIN MAX DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) UNIT V V I DC Input voltage range V V O DC output voltage range; output IG or OW state 0 V DC output voltage range; output 3-State T amb Operating ambient temperature range in free-air C t r, t f Input rise and fall times = 1.2 to 2.7V = 2.7 to 3.6V ns/v ABSOUTE MAXIMUM RATINGS 1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to (ground = 0V) SYMBO PARAMETER CONDITIONS RATING UNIT DC supply voltage 0.5 to +6.5 V I IK DC input diode current V I 0 50 ma V I DC input voltage Note to +6.5 V I OK DC output diode current V O or V O 0 50 ma DC output voltage; output IG or OW state Note to +0.5 V O DC output voltage; output 3-State Note to 6.5 I O DC output source or sink current V O = 0 to 50 ma I, I CC DC or current 100 ma T stg Storage temperature range 65 to +150 C Power dissipation per package P TOT plastic mini-pack (SO) above +70 C derate linearly with 8 mw/k 500 plastic shrink mini-pack (SSOP and TSSOP) above +60 C derate linearly with 5.5 mw/k 500 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. V mw 1998 Sep 24 5
6 DC EECTRICA CARACTERISTICS Over recommended operating conditions voltages are referenced to (ground = 0V) IMITS SYMBO PARAMETER TEST CONDITIONS Temp = -40 C to +85 C UNIT MIN TYP 1 MAX V I V I IG level Input voltage OW level Input voltage = 1.2V = 2.7 to 3.6V 2.0 V = 1.2V = 2.7 to 3.6V 0.8 V = 2.7V; V I = V I or V I ;I O = 12mA 0.5 V O IG level output voltage = 3.0V; V I = V I or V I ;I O = 100µA 0.2 V = 3.0V; V I = V I or V I; I O = 18mA 0.6 = 3.0V; V I = V I or V I; I O = 24mA 0.8 = 2.7V; V I = V I or V I ;I O = 12mA 0.40 V O OW level output voltage = 3.0V; V I = V I or V I ;I O = 100µA 0.20 V = 3.0V; V I = V I or V I; I O = 24mA 0.55 I I Input leakage current =36V; 3.6V; V I = 5.5V 5V or µa I OZ 3-State output OFF-state current = 3.6V; V I = V I or V I ;V O = 5.5V or µa I off Power off leakage supply = 0.0V; V I or V O = 5.5V µa I CC Quiescent supply current = 3.6V; V I = or ; I O = µa I CC Additional quiescent supply current per input pin = 2.7V to 3.6V; V I = 0.6V; I O = µa NOTES: 1. All typical values are at = 3.3V and T amb = 25 C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state Sep 24 6
7 AC CARACTERISTICS = 0V; t r = t f 2.5ns; C = 50pF; R = 500Ω; T amb = 40 C to +85 C. IMITS SYMBO PARAMETER WAVEFORM = 3.3V ±0.3V = 2.7V UNIT t P t P t P t PZ t PZ t PZ t PZ t W t W t SU t SU MIN TYP 1 MAX MIN MAX Propagation delay CP to Q n Figures 1, ns Propagation delay MR to Q n Figures 1, ns 3-State output enable time OE to Q n Figures 2, ns 3-State output disable time OE to Q n Figures 2, ns Clock pulse width IG or OW Figure ns Master Reset pulse width IG or OW Figure ns Setup time D n to CP Figure ns Setup time CE low before CP Figure ns t rem Removal time MR Figure ns t h old time IG or OW Dn after CP Figure ns t h old time CE OW before CP Figure ns f max Maximum clock pulse frequency Figure Mz NOTE: 1. Unless otherwise stated, all typical values are at = 3.3V and T amb = 25 C Sep 24 7
8 AC WAVEFORMS = 1.5V at 2.7V; = 0.5 at 2.7V. V O and V O are the typical output voltage drop that occur with the output load. V X = V O + 0.3V at 2.7V; V X = V O at 2.7V V Y = V O 0.3V at 2.7V; V Y = V O 0.1 at 2.7V 1/f max V I CP INPUT V I D n, CE INPUT t su t h ÉÉÉ ÉÉÉÉ ÉÉ t su t h V I CP INPUT t W V O Q n OUTPUT V O V O Q n OUTPUT t P t P NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00425 V O Figure 3. Data setup and hold times for the D n input and CE input to the CP input. SA00423 Figure 1. Clock (CP) to output (Q n ) propagation delays, the clock pulse width and the maximum clock pulse frequency. CP INPUT MR INPUT t rem t w V I OE INPUT t P OUTPUT OW to OFF OFF to OW V O t PZ t PZ V X t PZ t PZ Q n OUTPUT SA00519 Figure 4. Master reset pulse width, master reset to clock removal time, master reset to output propagation delay. V O OUTPUT IG to OFF OFF to IG outputs enabled V Y outputs disabled outputs enabled TEST CIRCUIT PUSE GENERATOR V I D.U.T. V O S 1 500Ω 2 x Open Figure 2. 3-State enable and disable times. SA00424 R T C 50pF 500Ω Test S 1 V I t P /t P Open 2.7V t PZ /t PZ 2 x 2.7V 3.6V 2.7V t PZ /t PZ SY00003 Figure 5. oad circuitry for switching times Sep 24 8
9 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT Sep 24 9
10 SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT Sep 24 10
11 TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT Sep 24 11
12 Data sheet status Data sheet status Product status Definition [1] Objective specification Preliminary specification Product specification Development Qualification Production This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. imiting values definition imiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers ife support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: Document order number: yyyy mmm dd 12
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INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC0 74C/CT/CU/CMOS ogic Family Specifications The IC0 74C/CT/CU/CMOS ogic Package Information The IC0 74C/CT/CU/CMOS ogic
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More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
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INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
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INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
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INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Infmation The IC06 74C/CT/CU/CMOS ogic
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