74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)

Size: px
Start display at page:

Download "74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)"

Transcription

1 INTEGRATED CIRCUITS inputs/outputs; positive-edge trigger (3-State) 1998 Sep 24

2 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7V to 3.6V Complies with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TT levels 9-bit positive edge-triggered register Independent register and 3-State buffer operation Flow-through pin-out architecture DESCRIPTION The is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TT families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The is a 9-bit D-type flip-flop with common clock (CP), Clock Enable (CE), Master Reset (MR) and 3-State outputs for bus-oriented applications. The nine flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the OW-to-IG CP transition provided CE is OW. When CE is IG the flip-flops hold their data. A OW on MR resets all flip-flops. When OE is OW, the contents of the nine flip-flops is available at the outputs. When OE is IG, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA = 0 V; T amb = 25 C; t r = t f 2.5 ns SYMBO PARAMETER CONDITIONS TYPICA UNIT Propagation delay 5.1 ns CP to Q n C = 50 pf; t P /t P Propagation delay = 3.3 V 5.2 ns MR to Q n C f max Maximum clock frequency = 50 pf; 150 Mz = 3.3 V C I Input capacitance 5.0 pf Power dissipation capacitance per C PD Notes 1 and 2 27 pf flip-flop NOTES: 1. C PD is used to determine the dynamic power dissipation (P D in µw) P D = C PD V 2 CC f i (C V 2 CC f o ) where: f i = input frequency in Mz; C = output load capacity in pf; f o = output frequency in Mz; = supply voltage in V; (C V 2 CC f o ) = sum of the outputs. 2. The condition is V I = to ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDERING CODE PKG. DWG. # 24-Pin Plastic SO 40 C to +85 C D SOT Pin Plastic SSOP Type II 40 C to +85 C DB SOT Pin Plastic TSSOP Type I 40 C to +85 C PW SOT Sep

3 PIN DESCRIPTION PIN NUMBER SYMBO NAME AND FUNCTION 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10 D 0 to D 8 Output enable input (active OW) Data inputs 11 MR Master reset (active OW) 12 Ground (0 V) 13 CP Clock pulse (active rising) 14 CE Clock enable (active OW) 23, 22, 21, 20, 19, 18, 17, 16, 15 Q 0 to Q 8 3-State flip-flop outputs 24 Positive supply voltage FUNCTION TABE OPERATING MODES INPUTS OE MR CE CP D n INTERNA FIP-FOPSFOPS OUTPUTS Clear X X X Q 0 to Q 8 oad and read register l h oad register and disable outputs X X l h Z Z old NC X NC NC = IG voltage level h = IG voltage level one set-up time prior to the OW-to-IG CP transition = OW voltage level l = OW voltage level one set-up time prior to the OW-to-IG CP transition Z = high impedance OFF-state = OW to IG clock transition NC= no change PIN CONFIGURATION OGIC SYMBO 11 1 OE 1 24 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 MR Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 CE 2 MR OE D 0 Q 0 3 D 1 Q 1 4 D 2 Q 2 5 D 3 Q 3 6 D 4 Q 4 7 D 5 Q 5 8 D 6 Q 6 9 D 7 Q 7 10 D 8 Q 8 CP CE CP SA SA Sep 24 3

4 OGIC SYMBO (IEEE/IEC) FUNCTIONA DIAGRAM EN R G1 1C D 0 D 1 D 2 D 3 Q 0 Q 1 Q 2 Q D D 4 D 5 FF0 to FF8 3 STATE OUTPUTS Q 4 Q D 6 Q D 7 Q D 8 Q CP CE MR OE SA00420 SA00421 OGIC DIAGRAM D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 MR D R Q CE CP CP CP CP CP CP CP CP CP FF0 FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 SA Sep 24 4

5 RECOMMENDED OPERATING CONDITIONS IMITS SYMBO PARAMETER CONDITIONS MIN MAX DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) UNIT V V I DC Input voltage range V V O DC output voltage range; output IG or OW state 0 V DC output voltage range; output 3-State T amb Operating ambient temperature range in free-air C t r, t f Input rise and fall times = 1.2 to 2.7V = 2.7 to 3.6V ns/v ABSOUTE MAXIMUM RATINGS 1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to (ground = 0V) SYMBO PARAMETER CONDITIONS RATING UNIT DC supply voltage 0.5 to +6.5 V I IK DC input diode current V I 0 50 ma V I DC input voltage Note to +6.5 V I OK DC output diode current V O or V O 0 50 ma DC output voltage; output IG or OW state Note to +0.5 V O DC output voltage; output 3-State Note to 6.5 I O DC output source or sink current V O = 0 to 50 ma I, I CC DC or current 100 ma T stg Storage temperature range 65 to +150 C Power dissipation per package P TOT plastic mini-pack (SO) above +70 C derate linearly with 8 mw/k 500 plastic shrink mini-pack (SSOP and TSSOP) above +60 C derate linearly with 5.5 mw/k 500 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. V mw 1998 Sep 24 5

6 DC EECTRICA CARACTERISTICS Over recommended operating conditions voltages are referenced to (ground = 0V) IMITS SYMBO PARAMETER TEST CONDITIONS Temp = -40 C to +85 C UNIT MIN TYP 1 MAX V I V I IG level Input voltage OW level Input voltage = 1.2V = 2.7 to 3.6V 2.0 V = 1.2V = 2.7 to 3.6V 0.8 V = 2.7V; V I = V I or V I ;I O = 12mA 0.5 V O IG level output voltage = 3.0V; V I = V I or V I ;I O = 100µA 0.2 V = 3.0V; V I = V I or V I; I O = 18mA 0.6 = 3.0V; V I = V I or V I; I O = 24mA 0.8 = 2.7V; V I = V I or V I ;I O = 12mA 0.40 V O OW level output voltage = 3.0V; V I = V I or V I ;I O = 100µA 0.20 V = 3.0V; V I = V I or V I; I O = 24mA 0.55 I I Input leakage current =36V; 3.6V; V I = 5.5V 5V or µa I OZ 3-State output OFF-state current = 3.6V; V I = V I or V I ;V O = 5.5V or µa I off Power off leakage supply = 0.0V; V I or V O = 5.5V µa I CC Quiescent supply current = 3.6V; V I = or ; I O = µa I CC Additional quiescent supply current per input pin = 2.7V to 3.6V; V I = 0.6V; I O = µa NOTES: 1. All typical values are at = 3.3V and T amb = 25 C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state Sep 24 6

7 AC CARACTERISTICS = 0V; t r = t f 2.5ns; C = 50pF; R = 500Ω; T amb = 40 C to +85 C. IMITS SYMBO PARAMETER WAVEFORM = 3.3V ±0.3V = 2.7V UNIT t P t P t P t PZ t PZ t PZ t PZ t W t W t SU t SU MIN TYP 1 MAX MIN MAX Propagation delay CP to Q n Figures 1, ns Propagation delay MR to Q n Figures 1, ns 3-State output enable time OE to Q n Figures 2, ns 3-State output disable time OE to Q n Figures 2, ns Clock pulse width IG or OW Figure ns Master Reset pulse width IG or OW Figure ns Setup time D n to CP Figure ns Setup time CE low before CP Figure ns t rem Removal time MR Figure ns t h old time IG or OW Dn after CP Figure ns t h old time CE OW before CP Figure ns f max Maximum clock pulse frequency Figure Mz NOTE: 1. Unless otherwise stated, all typical values are at = 3.3V and T amb = 25 C Sep 24 7

8 AC WAVEFORMS = 1.5V at 2.7V; = 0.5 at 2.7V. V O and V O are the typical output voltage drop that occur with the output load. V X = V O + 0.3V at 2.7V; V X = V O at 2.7V V Y = V O 0.3V at 2.7V; V Y = V O 0.1 at 2.7V 1/f max V I CP INPUT V I D n, CE INPUT t su t h ÉÉÉ ÉÉÉÉ ÉÉ t su t h V I CP INPUT t W V O Q n OUTPUT V O V O Q n OUTPUT t P t P NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00425 V O Figure 3. Data setup and hold times for the D n input and CE input to the CP input. SA00423 Figure 1. Clock (CP) to output (Q n ) propagation delays, the clock pulse width and the maximum clock pulse frequency. CP INPUT MR INPUT t rem t w V I OE INPUT t P OUTPUT OW to OFF OFF to OW V O t PZ t PZ V X t PZ t PZ Q n OUTPUT SA00519 Figure 4. Master reset pulse width, master reset to clock removal time, master reset to output propagation delay. V O OUTPUT IG to OFF OFF to IG outputs enabled V Y outputs disabled outputs enabled TEST CIRCUIT PUSE GENERATOR V I D.U.T. V O S 1 500Ω 2 x Open Figure 2. 3-State enable and disable times. SA00424 R T C 50pF 500Ω Test S 1 V I t P /t P Open 2.7V t PZ /t PZ 2 x 2.7V 3.6V 2.7V t PZ /t PZ SY00003 Figure 5. oad circuitry for switching times Sep 24 8

9 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT Sep 24 9

10 SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT Sep 24 10

11 TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT Sep 24 11

12 Data sheet status Data sheet status Product status Definition [1] Objective specification Preliminary specification Product specification Development Qualification Production This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. imiting values definition imiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers ife support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: Document order number: yyyy mmm dd 12

74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)

74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) INTEGRATED CIRCUITS inputs/outputs; positive edge-trigger (3-State) 1998 Jul 29 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7 to 3.6 Complies with

More information

74LVC573 Octal D-type transparent latch (3-State)

74LVC573 Octal D-type transparent latch (3-State) INTEGRATED CIRCUITS 74VC573 Supersedes data of February 1996 IC24 Data andbook 1997 Mar 12 74VC573 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance with JEDEC standard no. 8-1A Inputs accept

More information

74LV373 Octal D-type transparent latch (3-State)

74LV373 Octal D-type transparent latch (3-State) INTEGRATED CIRCUITS 74V373 Supersedes data of 1997 March 04 IC24 Data andbook 1998 Jun 10 74V373 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0V to 3.6V Accepts

More information

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28 INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower

More information

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground

More information

74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS

74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of February 1996 IC24 ata Handbook 1997 Mar 12 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance

More information

INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook

INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V

More information

74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger

74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger INTEGRATED IRUITS positive-edge trigger Supersedes data of 1996 Nov 07 I24 Data andbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0 to 3.6V Accepts

More information

74LV393 Dual 4-bit binary ripple counter

74LV393 Dual 4-bit binary ripple counter INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical

More information

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels

More information

74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS

74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of 1996 Feb IC24 ata Handbook 1997 Mar 20 FEATURES Wide operating voltage: 1.0 to 5.5 Optimized for Low oltage

More information

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels

More information

INTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook. INTEGRATED CIRCUITS Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20 FEATURES Optimized for low voltage applicatio: 1.0 to 3.6 V Accepts TTL input levels between = 2.7 V and = 3.6 V Typical

More information

INTEGRATED CIRCUITS. 74F85 4-bit magnitude comparator. Product specification 1994 Sep 27 IC15 Data Handbook. Philips Semiconductors

INTEGRATED CIRCUITS. 74F85 4-bit magnitude comparator. Product specification 1994 Sep 27 IC15 Data Handbook. Philips Semiconductors INTEGRATED CIRCUITS 1994 Sep 27 IC15 Data Handbook Philips Semiconductors FEATURES High-impedance NPN base inputs for reduced loading (20µA in High and ow states) Magnitude comparison of any binary words

More information

74ABT ABTH bit latched transceiver with dual enable and master reset (3-State)

74ABT ABTH bit latched transceiver with dual enable and master reset (3-State) INTEGRATED CIRCUITS 16-bit latched traceiver with dual enable Supersedes data of 1995 Sep 18 IC23 Data andbook 1998 Feb 27 FEATURES Two 8-bit octal traceivers with D-type latch ive iertion/extraction permitted

More information

74ABT899 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

74ABT899 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State) INTEGRATED CIRCUITS 9-bit dual latch traceiver with 8-bit parity Supersedes data of 993 Oct 4 IC23 Data andbook 998 Jan 6 9-bit dual latch traceiver with 8-bit parity FEATURES Symmetrical (A and B bus

More information

INTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors

INTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors INTEGRATED CIRCUITS Supersedes data of 2001 May 09 2002 Dec 13 Philips Semiconductors FEATURES General purpose and PCI-X 1:4 clock buffer 8-pin TSSOP package See PCK2001 for 48-pin 1:18 buffer part See

More information

74ALVCH bit universal bus transceiver (3-State)

74ALVCH bit universal bus transceiver (3-State) INTEGRATED CIRCUITS Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 24 FEATURES Complies with JEDEC standard no. 8-1A CMOS low power coumption Direct interface with TTL levels Current drive

More information

DATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

DATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Supersedes data of 1998 Mar 17 2003 Dec 12 FEATURES 5 V tolerant inputs/outputs for interfacing

More information

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible

More information

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver. 16-bit dual supply translating transciever; 3-state Rev. 02 1 June 2004 Product data sheet 1. General description 2. Features The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior

More information

8-bit binary counter with output register; 3-state

8-bit binary counter with output register; 3-state Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It

More information

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance

More information

INTEGRATED CIRCUITS. 74F521 8-bit identity comparator. Product specification May 15. IC15 Data Handbook

INTEGRATED CIRCUITS. 74F521 8-bit identity comparator. Product specification May 15. IC15 Data Handbook INTEGRATED CIRCUITS 1990 May IC Data Handbook FEATURES Compares two 8-bit words in 6.5ns typical Expandable to any word length DESCRIPTION The is an expandable 8-bit comparator. It compares two words of

More information

DATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

DATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET 16-bit D-type transparent latch with 5 V Supersedes data of 2002 Oct 02 2003 Dec 08 FEATURES 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage

More information

INTEGRATED CIRCUITS. 74F154 1-of-16 decoder/demultiplexer. Product specification Jan 08. IC15 Data Handbook

INTEGRATED CIRCUITS. 74F154 1-of-16 decoder/demultiplexer. Product specification Jan 08. IC15 Data Handbook INTEGRATED CIRCUITS 1-of-16 decoder/demultiplexer 1990 Jan 08 IC15 Data Handbook Decoder/demultiplexer FEATURES 16-line demultiplexing capability Mutually exclusive outputs 2-input enable gate for strobing

More information

The 74HC21 provide the 4-input AND function.

The 74HC21 provide the 4-input AND function. Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

8-bit serial-in/parallel-out shift register

8-bit serial-in/parallel-out shift register Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.

More information

INTEGRATED CIRCUITS. 74F804, 74F1804 Hex 2-input NAND drivers. Product specification Sep 14. IC15 Data Handbook

INTEGRATED CIRCUITS. 74F804, 74F1804 Hex 2-input NAND drivers. Product specification Sep 14. IC15 Data Handbook INTEGRATED CIRCUITS F0, F0 0 Sep IC5 Data Handbook F0/0 FEATURES High capacitive drive capability Choice of configuration Corner V CC and GND F0 Center V CC and GND F0 Typical propagation delay of.5ns

More information

PHILIPS 74LVT transparent D-type latch datasheet

PHILIPS 74LVT transparent D-type latch datasheet PIIPS transparent -type latch datasheet http://www.manuallib.com/philips/74lvt162373-transparent-d-type-latch-datasheet.html The is a high-performance BiCMOS product designed for VCC operation at 3.3 V.

More information

Hex inverting Schmitt trigger with 5 V tolerant input

Hex inverting Schmitt trigger with 5 V tolerant input Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible

More information

74F393 Dual 4-bit binary ripple counter

74F393 Dual 4-bit binary ripple counter INTEGRATED CIRCUITS 1988 Nov 01 IC15 Data Handbook FEATURES Two 4-bit binary counters Two Master Resets to clear each 4-bit counter individually PIN CONFIGURATION CPa 1 MRa 2 14 13 V CC CPb DESCRIPTION

More information

Octal buffer/line driver (3-State)

Octal buffer/line driver (3-State) FEATURES Octal bus interface Functio similar to the ABT4 Provides ideal interface and increases fan-out of MOS Microprocessors Efficient pinout to facilitate PC board layout 3-State buffer outputs sink

More information

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground). Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and

More information

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses. Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance

More information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 27 the former NP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, ogic and

More information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, ogic

More information

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

More information

74HC1G125; 74HCT1G125

74HC1G125; 74HCT1G125 Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky

More information

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC164; 74HCT bit serial-in, parallel-out shift register Rev. 03 4 pril 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They

More information

INTEGRATED CIRCUITS. 74ALS30A 8-Input NAND gate. Product specification 1991 Feb 08 IC05 Data Handbook

INTEGRATED CIRCUITS. 74ALS30A 8-Input NAND gate. Product specification 1991 Feb 08 IC05 Data Handbook INTEGRATED CIRCUITS -Input NAND gate 1991 Feb 0 IC05 Data Handbook TPE TPICAL PROPAGATION DELA TPICAL SUPPL CURRENT (TOTAL) 5.0ns 0.5mA PIN CONFIGURATION A 1 B 2 14 13 V CC NC ORDERING INFORMATION C 3

More information

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop. Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.

More information

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23 INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23 FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified

More information

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs. Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

More information

14-stage binary ripple counter

14-stage binary ripple counter Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.

More information

INTEGRATED CIRCUITS. 74ALS138 1-of-8 decoder/demultiplexer. Product specification 1996 Jul 03 IC05 Data Handbook

INTEGRATED CIRCUITS. 74ALS138 1-of-8 decoder/demultiplexer. Product specification 1996 Jul 03 IC05 Data Handbook INTEGRATED CIRCUITS 1996 Jul 03 IC05 Data Handbook FEATURES Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding DESCRIPTION The decoder accepts three

More information

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The

More information

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

PHILIPS 74ALVT16245 transceiver datasheet

PHILIPS 74ALVT16245 transceiver datasheet PHILIPS traceiver datasheet http://www.manuallib.com/philips/74alvt16245-traceiver-datasheet.html The is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility

More information

74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State)

74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) INTGRAT CIRCUITS Supersedes data of 1995 Aug 03 IC23 ata andbook 1998 Feb 27 FATURS 16-bit traparent latch Multiple V CC and GN pi minimize switching noise Power-up 3-State ive iertion/extraction permitted

More information

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC244; 74HCT244. Octal buffer/line driver; 3-state Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

More information

74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state

74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 03 21 pril 2009 Product data sheet 1. General description 2. Features 3. pplications The is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

74ALVT V/3.3V 16-bit transparent D-type latch (3-State) INTEGRATED CIRCUITS

74ALVT V/3.3V 16-bit transparent D-type latch (3-State) INTEGRATED CIRCUITS INTGRAT CIRCUITS 2.V/3.3V 16-bit traparent -type latch (3-State) Supersedes data of 1998 Feb 13 IC23 ata andbook 1999 Oct 18 2.V/3.3V 16-bit traparent -type latch (3-State) FATURS 16-bit traparent latch

More information

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance

More information

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output

More information

DATA SHEET. 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state INTEGRATED CIRCUITS

DATA SHEET. 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state INTEGRATED CIRCUITS INTEGRTE CIRCUITS T SHEET Octal -type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Supersedes data of 2003 Jun 20 2004 Mar 22 FETURES 5 V tolerant inputs and outputs, for

More information

2-input EXCLUSIVE-OR gate

2-input EXCLUSIVE-OR gate Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output

More information

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02. Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC

More information

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer

More information

DATA SHEET. 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger INTEGRATED CIRCUITS

DATA SHEET. 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger INTEGRATED CIRCUITS INTEGRTED IRUITS DT SHEET Supersedes data of 1998 pr 28 2004 Mar 18 FETURES 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 to 3.6 V MOS low power consumption Direct

More information

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86. Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0

More information

The 74LVC1G02 provides the single 2-input NOR function.

The 74LVC1G02 provides the single 2-input NOR function. Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use

More information

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26.

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26. INTEGRTED CIRCUITS DT SHEET Quad 2-input NND gate Supersedes data of 1997 ug 26 2003 Jun 30 Quad 2-input NND gate FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds

More information

The 74LVC1G11 provides a single 3-input AND gate.

The 74LVC1G11 provides a single 3-input AND gate. Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC0 74C/CT/CU/CMOS ogic Family Specifications The IC0 74C/CT/CU/CMOS ogic Package Information The IC0 74C/CT/CU/CMOS ogic

More information

7-stage binary ripple counter

7-stage binary ripple counter Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).

More information

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device. 74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function

More information

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at   ore.hu. EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec 01 2003 Jul 25 FETURES

More information

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation: Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

5-stage Johnson decade counter

5-stage Johnson decade counter Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Infmation The IC6 74C/CT/CU/CMOS ogic

More information

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Infmation The IC06 74C/CT/CU/CMOS ogic

More information

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state Rev. 2 16 March 2015 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1. Rev. 2 24 March 25 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features

More information

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1. Rev. 1 17 November 25 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers. Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0

More information

8-bit parallel-in/serial-out shift register

8-bit parallel-in/serial-out shift register Rev. 7 9 March 2016 Product data sheet 1. General description The is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When

More information

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger Rev. 4 12 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and

More information

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive

More information

74LV General description. 2. Features. 8-bit addressable latch

74LV General description. 2. Features. 8-bit addressable latch Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed

More information

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1. Rev. 3 28 April 26 Product data sheet. Product profile. General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology..2 Features Logic level

More information

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11.

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11. DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D186 Supersedes data of 1999 Apr 27 2004 Oct 11 FEATURES Low current (max. 200 ma) Low voltage (max. 15 V). APPLICATIONS High-speed switching. PINNING

More information

Distributed by: www.jameco.com 1-800-831-42 The content and copyrights of the attached material are the property of its owner. INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download:

More information

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. Rev. 3 16 August 2013 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 5 9 July 2012 Product data sheet 1. General description The is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

More information

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20 DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D19 Supersedes data of 1997 Jun 2 22 May 22 FEATURES Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown. APPLICATIONS Line

More information

74LVC823A-Q General description. 2. Features and benefits

74LVC823A-Q General description. 2. Features and benefits 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 1 15 September 2016 Product data sheet 1. General description The is a 9-bit D-type flip-flop with common clock

More information

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads; Rev. 06 4 June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD)

More information