LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

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1 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter V DD In order to determine the propagation delay time, it is necessary to know when the second stage of the two-stage + M6 comparator begins to turn on. v in i - 6 v Second stage: out Trip point: Assume that M6 and are saturated. (We know that the steepest slope occurs for this condition.) Equate i 6 to i 7 and solve for v in which becomes the trip point. K N (W 7 /L 7 ) v in V TRP V DD - V TP - K P (W 6 /L 6 ) (V Bias- V SS -V TN ) Example: If W 7 /L 7 W 6 /L 6, V DD 2.5V, V SS -2.5V, and V Bias 0V the trip point for the circuit above is V TRP /50 ( ) V V Bias V SS i 7 Fig Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator Previously we calculated the propagation delay time for a nonslewing comparator. If the comparator slews, then the propagation delay time is found from dv i i i C i dt i C v i i t i where C i is the capacitance to ground at the output of the i-th stage The propagation delay time of the i-th stage is, V i t i t i C i I i The propagation delay time is found by summing the delays of each stage. t p t 1 + t 2 + t 3 +

2 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Propagation Time Delay of a Two-Stage, Open-Loop Comparator For the two-stage comparator shown V DD 2.5V assume that C I 0.2pF and C II 5pF. M3 M4 M6 Also, assume that v G1 0V and that v G2 has the waveform shown. If the input v o1 voltage is large enough to cause slew to dominate, find the propagation time delay 30µA M1 M2 C I v G1 3µm 3µm 0.2pF of the rising and falling output of the comparator and give the propagation time delay of the comparator. v G2 234µA 2.5V 0V -2.5V v G t(µs) Fig Solution 1.) Total delay sum of the first and second stage delays, t 1 and t 2 2.) First, consider the change of v G2 from -2.5V to 2.5V at 0.2µs. The last row of Table gives v o1 +2.5V and v out -2.5V 3.) t f1, requires C I, V o1, and I 5. C I 0.2pF, I 5 30µA and V 1 can be calculated by finding the trip point of the output stage/ M8 M5 30µA V SS -2.5V 38µm v out 35µm C II 5pF Fig A Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Continued 4.) The trip point of the output stage by setting the current of M6 when saturated equal to 234µA. β 6 2 (V SG6 - V TP ) µA V SG V Therefore, the trip point of the second stage is V TRP V Therefore, V 1 2.5V V V SG V. Thus the falling propagation time delay of the first stage is 1.035V t fo1 0.2pF 30µA 6.9ns 5.) The rising propagation time delay of the second stage requires C II, V out, and I 6. C II is given as 5pF, V out 2.5V (assuming the trip point of the circuit connected to the output of the comparator is 0V), and I 6 can be found as follows: V G6 (guess) 0.5[V G6 (I 6 234µA) + V G6 (min)] 2 15 V G6 (min) V G1 - V GS1 (I SS /2) + V DS2 -V GS1 (I SS /2) V V G6 (guess) 0.5(1.465V-1.00V) 0.232V Therefore V SG6 2.27V and I 6 β 6 2 (V SG6 - V TP ) ( )2 2,342µA

3 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Continued 6.) The rising propagation time delay for the output can expressed as 2.5V t rout 5pF 2,342µA-234µA 5.93ns Thus the total propagation time delay of the rising output of the comparator is approximately 12.8ns and most of this delay is attributable to the first stage. 7.) Next consider the change of v G2 from 2.5V to -2.5V which occurs at 0.4µs. We shall assume that v G2 has been at 2.5V long enough for the conditions of Table to be valid. Therefore, v o1 V SS -2.5V and v out V DD. The propagation time delays for the first and second stages are calculated as 3V 1.465V-(-1.13V) v out t ro1 0.2pF 30µA 17.3ns 2V 2.5V t fout 5pF 234µA 53.42ns 8.) The total propagation time delay of the falling output is 70.72ns. Taking the average of the rising and falling propagation time delays gives a propagation time delay for this two-stage, open-loop comparator of about 41.76ns. 1V 0V -1V -2V V TRP V v o1 Falling prop. delay time Rising prop. delay time -3V 200ns 300ns 400ns 500ns 600ns Time Fig Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Design of a Two-Stage, Open-Loop Comparator Table Design of the Two-Stage, Open-Loop Comparator of Fig for a Linear Response. Specifications: t p, C II,V in (min), V OH, V OL, V icm +, Vicm -, and overdrive Constraints: Technology, VDD and V SS Step Design Relationships Comments 1 p I p II 1 t p mk, and I 7 I 6 p II C II λ N +λ P Choose m 1 2 W 6 2 I 6 L 6 K P (V SD6 (sat)) 2 and W 7 L7 2 I 7 K N (V DS7 (sat)) 2 V SD6 (sat) V DD -V OH V DS7 (sat) V OL - V SS 3 2C I A result of choosing m 1. Guess C I as 0.1pF to 0.5pF I 5 I 7 C II Will check C I later 4 W 3 L W 4 I 5 V 3 L SG3 V DD -V + icm +VTN 4 K P (V SG3 - V TP ) 2 5 A v (0)(g ds2 +g ds4 )(g ds6 +g ds7 ) W 1 W 2 g m1 2 g m1 g m6 L 1 L g 2 K N I m6 5 6 Find C I and check assumption C I C gd2 +C gd4 +C gs6 +C bd2 +C bd4 7 W V DS5 (sat) V - 5 icm -VGS1 -V SS L 5 2K P W 6 I 6 L 6 A v (0) V OH +V OL V in (min) If C I is greater than the guess in step 3, then increase C I and repeat steps 4 through 6 2 I 5 If V DS5 (sat) is less than 100mV, increase W 1 /L 1. K N (V DS5 (sat)) 2

4 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Two-Stage, Open-Loop Comparator Design for a Linear Response. Assume the specifications of the V DD comparator shown are given below. t p 50ns V OH 2V V OL -2V i3 i 4 V DD 2.5V V SS -2.5V C II 5pF M3 M4 v o1 V in (min) 1mV V icm + 2V V icm V Also assume that the overdrive will be a factor of 10. Use this architecture to achieve the above specifications and assume that all I SS + channel lengths are to be. VBias Solution - Following the procedure outlined in Table 8.2-2, we choose m 1 to get 10 p I p II x106 rads/sec This gives I 6 I x10 6 5x µA I 6 I 7 400µA Therefore, W 6 L (0.5) andw 7 L 7 v G1 M1 M (0.5) i 1 i 2 C I M5 V SS v G2 M6 C II v out Fig Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Continued Next, we guess C I 0.2pF. This gives I 5 32µA and we will increase it to 40µA for a margin of safety. Step 4 gives V SG3 as 1.2V which results in W 3 W ( )2 3.2 W 3 W 4 4 The desired gain is found to be 4000 which gives an input transconductance of g m µS This gives the W/L ratios of M1 and M2 as W 1 L W 2 1 L (162) W 1 L W 2 1 L 6 2 To check the guess for C I we need to calculate it which is done as C I C gd2 +C gd4 +C gs6 +C bd2 +C bd4 0.9fF+1.3fF+119.5fF+20.4fF+36.8fF 178.9fF which is less than what was guessed so we will make no changes.

5 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Continued Finally, the W/L value of M5 is found by finding V GS1 as 0.946V which gives V DS5 (sat) 0.304V. This gives W L 5 (0.304) Obviously, M5 and cannot be connected gate-gate and source-source. The value of I 5 and I 7 must be derived separately as illustrated below. The W values are summarized below assuming that all channel lengths are. W 1 W 2 6µm W 3 W 4 4µm W 5 8µm W 6 64µm W 7 29µm V DD 2/1 10µA M8 2/1 M9 M10 10µA M5 2/1 8/1 M11 40µA 40µA M12 8/1 3/1 400µA 29/1 V SS Fig Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Design of a Two-Stage Comparator for a Slewing Response Table Two-Stage, Open-Loop Comparator Design for a Slewing Response. Specifications: t p, C II,V in (min), V OH, V OL, V icm +, Vicm - Constraints: Technology, V DD and V SS Step Design Relationships Comments 1 II dv out I 7 I 6 C dt C II (V OH -V OL ) Assume the trip point of the output is (V OH - t p V OL )/2. 2 W 6 2 I 6 L 6 K P (V SD6 (sat)) 2 and W 7 L7 2 I 7 K N (V DS7 (sat)) 2 V SD6 (sat) V DD -V OH V DS7 (sat) V OL - V SS 3 2C I Typically 0.1pf<C I <0.5pF Guess C I as 0.1pF to 0.5pF I 5 I 7 C II 4 I dv o1 I 5 C dt C I (V OH -V OL ) Assume that v o1 swings between V OH and t p V OL. 5 W 3 L W 4 I 5 V 3 L SG3 V DD -V + icm +VTN 4 K P (V SG3 - V TP ) 2 6 g m1 A v (0)(g ds2 +g ds4 )(g ds6 +g ds7 ) W 1 g m6 L W 2 1 L g m1 2 g 2 K N I m6 5 7 Find C I and check assumption C I C gd2 +C gd4 +C gs6 +C bd2 +C bd4 8 2K P W 6 I 6 L 6 A v (0) V OH +V OL V in (min) If C I is greater than the guess in step 3, increase the value of C I and repeat steps 4 through 6 W V DS5 (sat) V I 5 If V DS5 (sat) is less than 100mV, increase W 1 /L 1. icm -VGS1 -V SS L 5 K N (V DS5 (sat)) 2

6 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Two-Stage, Open-Loop Comparator Design for a Slewing Response Assume the specifications of Fig are given below. t p 50ns V OH 2V V OL -2V V DD 2.5V V SS -2.5V C II 5pF V in (min) 1mV V icm + 2V V icm V Design a two-stage, open-loop comparator using the circuit of Fig to the above specifications and assume all channel lengths are to be. Solution Following the procedure outlined in Table 8.2-3, we calculate I 6 and I 7 as I 6 I 7 5x x µA Therefore, W L 6 (0.5) andw L 7 (0.5) Next, we guess C I 0.2pF. This gives I 5 0.2pF(4V) 50ns 16µA I 5 20µA Step 5 gives V SG3 as 1.2V which results in W 3 W ( ) W 3 W 4 2 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page Example Continued The desired gain is found to be 4000 which gives an input transconductance of g m µS This gives the W/L ratios of M1 and M2 as W 3 L W 4 3 L (81) W 1 L W 2 1 L 2 2 To check the guess for C I we need to calculate it which done as C I C gd2 +C gd4 +C gs6 +C bd2 +C bd4 0.9fF+0.4fF+119.5fF+20.4fF+15.3fF 156.5fF which is less than what was guessed. Finally, the W/L value of M5 is found by finding V GS1 as 1.00V which gives V DS5 (sat) 0.25V. This gives W L 5 (0.25) As in the previous example, M5 and cannot be connected gate-gate and sourcesource and a scheme like that of Example must be used. The W values are summarized below assuming that all channel lengths are. W 1 W 2 2µm W 3 W 4 4µm W 5 6µm W 6 64µm W 7 29µm

7 Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page SUMMARY The two-stage, open-loop comparator has two poles which should as large as possible The transient response of a two-stage, open-loop comparator will be limited by either the bandwidth or the slew rate It is important to know the initial states of a two-stage, open-loop comparator when finding the propagation delay time If the comparator is gainbandwidth limited then the poles should be as large as possible for minimum propagation delay time If the comparator is slew rate limited, then the current sinking and sourcing ability should be as large as possible