6.2 INTRODUCTION TO OP AMPS
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1 Introduction to Op Amps (7/17/00) Page INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis of both BJT and MOS op amps 3.) Illustrate the design of both BJT and MOS op amps Outline Introduction and Characterization of Op Amps Compensation of Op Amps General principles Miller, Nulling Miller Selfcompensation Feedforward Simple Op Amps Twostage Foldedcascode Design of Op Amps Summary ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
2 Introduction to Op Amps (7/17/00) Page 2 INTRODUCTION AND CHARACTERIZATION OF OP AMPS HighLevel Viewpoint of an Op Amp Block diagram of a general, twostage op amp: Compensation Circuitry v 1 v 2 Differential Transconductance Stage High Gain Stage v OUT Output Buffer v OUT ' Bias Circuitry Fig Differential transconductance stage: Forms the input and sometimes provides the differentialtosingle ended conversion. High gain stage: Provides the voltage gain required by the op amp together with the input stage. Output buffer: Used if the op amp must drive a low resistance. Compensation: Necessary to keep the op amp stable when resistive negative feedback is applied. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
3 Introduction to Op Amps (7/17/00) Page 3 Ideal Op Amp Symbol: v 1 i 1 V DD i 2 v i V SS v OUT = A v (v 1 v 2 ) v 2 Fig Null port: If the differential gain of the op amp is large enough then input terminal pair becomes a null port. A null port is a pair of terminals where the voltage is zero and the current is zero. I.e., v 1 v 2 = v i = 0 and i 1 = 0 and i 2 = 0 Therefore, ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current flows into or out of the differential inputs. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
4 Introduction to Op Amps (7/17/00) Page 4 General Configuration of the Op Amp as a Voltage Amplifier R 1 R2 v inn v inp v 2 v 1 vout Fig Noniverting voltage amplifier: v inn = 0 = R 1 R 2 R 1 v inp Inverting voltage amplifier: R 2 v inp = 0 = R 1 v inn ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
5 Introduction to Op Amps (7/17/00) Page 5 Example 1 Simplified Analysis of an Op Amp Circuit The circuit shown below is an inverting voltage amplifier using an op amp. Find the voltage transfer function, /v in. R 1 i 1 i 2 R 2 i i v in v i v out Virtual Ground Fig Solution If the differential voltage gain, A v, is large enough, then the negative feedback path through R 2 will cause the voltage v i and the current i i shown on Fig to both be zero. Note that the null port becomes the familiar virtual ground if one of the op amp input terminals is on ground. If this is the case, then we can write that and i 1 = v in R 1 i 2 = R 2 Since, i i = 0, then i 1 i 2 = 0 giving the desired result as v in = R 2 R 1. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
6 Introduction to Op Amps (7/17/00) Page 6 Linear and Static Characterization of the Op Amp A model for a nonideal op amp that includes some of the linear, static nonidealities: v 2 v 1 CMRR R icm V OS I B2 * i n 2 e n 2 * C id R id R out vout v 1 Ideal Op Amp R icm I B1 where R id = differential input resistance C id = differential input capacitance R icm = common mode input resistance V OS = inputoffset voltage I B1 and I B2 = differential inputbias currents I OS = inputoffset current (I OS = I B1 I B2 ) CMRR = commonmode rejection ratio e 2 n = voltagenoise spectral density (meansquare volts/hertz) Fig i 2 n = currentnoise spectral density (meansquare amps/hertz) ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
7 Introduction to Op Amps (7/17/00) Page 7 Linear and Dynamic Characteristics of the Op Amp Differential and commonmode frequency response: V out (s) = A v (s)[v 1 (s) V 2 (s)] ± A c (s) V 1 (s)v 2 (s) 2 Differentialfrequency response: A v (s) = s p 1 1 A v0 s p 1 2 s p 1 3 = A v0 p 1 p 2 p 3 (s p 1 )(s p 2 )(s p 3 ) where p 1, p 2, p 3, are the poles of the differentialfrequency response. 20log10(A v0 ) A v (jω) db Asymptotic Magnitude Actual Magnitude 6dB/oct. GB 0dB ω 1 ω 2 ω 3 ω 12dB/oct. 18dB/oct. Fig ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
8 Introduction to Op Amps (7/17/00) Page 8 Other Characteristics of the Op Amp Power supply rejection ratio (PSRR): PSRR = V DD V OUT A v (s) = V o/v in (V dd = 0) V o /V dd (V in = 0) Input common mode range (ICMR): ICMR = the voltage range over which the input commonmode signal can vary without influence the differential performance Slew rate (SR): SR = output voltage rate limit of the op amp Settling time (T s ): T s = time needed for the output of the op amp to reach a final value to with a predetermined tolerance when excited by a small signal. (SR is large signal excitation) v IN v OUT v OUT (t) Final Value ε Final Value Final Value ε ε ε Upper Tolerance Lower Tolerance Settling Time 0 0 T s t Fig ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
9 Introduction to Op Amps (7/17/00) Page 9 Classification of CMOS Op Amps Categorization of op amps: Conversion Hierarchy Voltage to Current Current to Voltage Classic Differential Amplifier Differentialtosingle ended Load (Current Mirror) Modified Differential Amplifier Source/Sink Current Loads MOS Diode Load First Voltage Stage Voltage to Current Current to Voltage Transconductance Grounded Gate Class A (Source or Sink Load) Transconductance Grounded Source Class B (PushPull) Current Stage Second Voltage Stage Table 6.11 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
10 Introduction to Op Amps (7/17/00) Page 10 TwoStage Op Amp Architecture Simple twostage op amp broken into voltagetocurrent and currenttovoltage stages: V DD V CC M3 M4 M6 Q3 Q4 Q6 v in M1 M2 v in v in Q1 Q2 VBias V I M5 I V V I I V M7 V SS VBias V I Q5 Q7 I V V I I V V EE OA01 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
11 Introduction to Op Amps (7/17/00) Page 11 FoldedCascode Op Amp Architecture Simple foldedcascode op amp broken into voltagetocurrent and currenttovoltage stages: V DD V CC V Bias M3 M10 M11 V Bias Q3 Q10 Q11 v in M1 M2 V Bias M6 M7 M8 M9 vout v in v in Q1 Q2 V Bias Q6 Q7 Q8 Q9 vout V Bias M4 M5 V I I I I V V SS V EE V Bias Q4 Q5 V I I I I V OA015 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
12 Introduction to Op Amps (7/17/00) Page 12 COMPENSATION OF OP AMPS GENERAL PRINCIPLES Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp. Types of Compensation 1. Miller Use of a capacitor feeding back around a highgain, inverting stage. Miller capacitor only Miller capacitor with an unitygain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Feedforward Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity. 3. Self compensating Load capacitor compensates the op amp. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
13 Introduction to Op Amps (7/17/00) Page 13 SingleLoop, Negative Feedback Systems V in (s) Σ F(s) A(s) V out (s) Fig A(s) = amplifier gain (normally the differentialmode voltage gain of the op amp) F(s) = transfer function of the external feedback from the output of the op amp back to the input. Definitions: Openloop gain = L(s) = A(s)F(s) Closedloop gain = V out (s) V in (s) = A(s) 1A(s)F(s) Stability Requirements: The requirements for stability for a singleloop, negative feedback system is, A(jω 0 )F(jω 0 ) = L(jω 0 ) < 1 where ω 0 is defined as Arg[ A(jω 0 )F(jω 0 )] = Arg[L(jω 0 )] = 0 Another convenient way to express this requirement is Arg[ A(jω 0dB )F(jω 0dB )] = Arg[L(jω 0dB )] > 0 where ω 0dB is defined as A(jω 0dB )F(jω 0dB ) = L(jω 0dB ) = 1 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
14 Introduction to Op Amps (7/17/00) Page 14 Illustration of the Stability Requirement using Bode Plots Arg[A(jω)F(jω)] A(jω)F(jω) 0dB dB/decade ω 40dB/decade Φ M ω 0dB Frequency (rads/sec.) ω Fig A measure of stability is given by the phase when A(jω)F(jω) = 1. This phase is called phase margin. Phase margin = Φ M = Arg[A(jω 0dB )F(jω 0dB )] = Arg[L(jω 0dB )] ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
15 Introduction to Op Amps (7/17/00) Page 15 Why Do We Want Good Stability? Consider the step response of secondorder system which closely models the closedloop gain of the op amp. (t) A v ω o t = ω n t (sec.) Fig A good step response is one that quickly reaches its final value. Therefore, we see that phase margin should be at least 45 and preferably 60 or larger. (A good rule of thumb for satisfactory stability is that there should be less than three rings.) ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
16 Introduction to Op Amps (7/17/00) Page 16 Uncompensated Frequency Response of TwoStage Op Amps TwoStage Op Amps: V DD V CC M3 M4 M6 Q3 Q4 Q6 v in M1 M2 v in Q1 Q2 SmallSignal Model: VBias M5 V SS M7 VBias Q5 V EE Q7 OA016 g m1 v in 2 D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7) R 1 C 1 v1 g m2v in 2 g m4 v 1 R 2 C v2 R 3 C 3 2 gm6 v 2 Note that this model neglects the basecollector and gatedrain capacitances for purposes of simplification. OA03 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
17 Introduction to Op Amps (7/17/00) Page 17 Uncompensated Frequency Response of TwoStage Op Amps Continued For the MOS twostage op amp: R g r ds3 r ds1 m3 g R 2 = r ds2 r ds4 and R 3 = r ds6 r ds7 m3 C 1 = C gs3 C gs4 C bd1 C bd3 C 2 = C gs6 C bd2 C bd4 and C 3 = C L C bd6 C bd7 For the BJT twostage op amp: R 1 = 1 1 g r π3 r π4 r o3 m3 g R 2 = r π6 r o2 r o4 r π6 and R 3 = r o6 r o7 m3 C 1 = C π3 C π4 s1 s3 C 2 = C π6 s2 s4 and C 3 = C L s6 s7 Assuming the pole due to C 1 is much greater than the poles due to C 2 and C 3 gives, g m1 v in R 2 C v2 R 3 C 3 2 gm6 v 2 The locations for the two poles are given by the following equations p 1 = 1 1 R I C and p 2 = I R II C II g m1 V in V V out R I C I R II C II I gmii V I OA045 where R I (R II ) is the resistance to ground seen from the output of the first (second) stage and C I (C II ) is the capacitance to ground seen from the output of the first (second) stage. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
18 Introduction to Op Amps (7/17/00) Page 18 Uncompensated Frequency Response of an Op Amp A vd (0) db 20dB/decade Arg[A(jω)] A(jω) 0dB Phase Shift /decade p 1 ' GB 45 /decade p 2 ' log 10 (ω) 40dB/decade log 10 (ω) ω 0dB Fig If we assume that F(s) = 1 (this is the worst case for stability considerations), then the above plot is the same as the loop gain. Note that the phase margin is much less than 45. Therefore, the op amp must be compensated before using it in a closedloop configuration. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
19 Introduction to Op Amps (7/17/00) Page 19 MILLER COMPENSATION TwoStage Op Amp V DD V CC M3 C M M4 M6 Q3 Q4 C M Q6 M1 M2 v in C I C II v in Q1 Q2 C I C II VBias M5 V SS M7 VBias Q5 V EE Q7 OA046 The various capacitors are: = accomplishes the Miller compensation C M = capacitance associated with the firststage mirror (mirror pole) C I = output capacitance to ground of the firststage C II = output capacitance to ground of the secondstage ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
20 Introduction to Op Amps (7/17/00) Page 20 Simplification of the Compensated TwoStage, SmallSignal Frequency Response Model Use the CMOS op amp to illustrate: 1.) Assume that g m3 >> g ds3 g ds1 2.) Assume that g m3 C M >> GB Therefore, v 1 v2 g m1 v in 2 1 g m2 v in r ds1 r ds3 C M g m3 2 g m4 v 1 C 1 rds2 r ds4 g m6 v 2 r ds6 r ds7 C L v in v 2 g m1 v in CI rds2 r ds4 g m6 v C 2 II rds6 r ds7 Same circuit holds for the BJT op amp with different component relationships. Fig. 6.25B ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
21 Introduction to Op Amps (7/17/00) Page 21 General TwoStage Frequency Response Analysis V in g mi V in C I RI gmii V 2 R II C II V out Nodal Equations: Fig where g mi = g m1 = g m2, R I = r ds2 r ds4, C I = C 1 and g mii = g m6, R II = r ds6 r ds7, C II = C 2 = C L g mi V in = [G I s(c I )]V 2 [s ]V out and 0 = [g mii s ]V 2 [G II sc II s ]V out Solving using Cramer s rule gives, V out (s) V in (s) = g mi (g mii s ) G I G II s [G II (C I C II )G I (C II )g mii ]s 2 [C I C II C I C II ] A o [1 = s ( /g mii )] 1s [R I (C I C II )R II (C 2 )g mii R 1 R II ]s 2 [R I R II (C I C II C I C II )] where, A o = g mi g mii R I R II In general, D(s) = 1 s p 1 1 s p = 1 s 1 2 p 1 s 1 p 2 2 p 1 p 2 p 1 = 1 1 R I (C I C II )R II (C II )g mii R 1 R II C c g mii R 1 R II C, z = g mii c p 2 = [R I (C I C II )R II (C II )g mii R 1 R II ] R I R II (C I C II C I C II ) D(s) 1 s s p 2 1 p 1 p, if p 2 >> p 1 2 g mii C I C II C I C II g mii C II where C II > > C I. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
22 Introduction to Op Amps (7/17/00) Page 22 Summary of Results for Miller Compensation of the TwoStage Op Amp There are three roots of importance: 1.) Righthalf plane zero: This root is very undesirable because it boosts the loop magnitude while decreasing the phase. 2.) Dominant lefthalf plane pole (the Miller pole): z 1 = g mii = g m6 1 p 1 g mii R I R II C = (g ds2 g ds4 )(g ds6 g ds7 ) c g m6 This root accomplishes the desired compensation. 3.) Lefthalf plane output pole: p 2 g mii C g m6 II C L This pole must be beyond the unitygainbandwidth or the phase margin will not be satisfied. Root locus plot of the Miller compensation: Closedloop poles, 0 Openloop poles =0 jω σ p 2 p 2 ' p 1 ' p 1 z 1 Fig. 6.27A ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
23 Introduction to Op Amps (7/17/00) Page 23 Compensated OpenLoop Frequency Response of the TwoStage Op Amp A(jω)F(jω) A vd (0) db Compensated Uncompensated 20dB/decade Arg[A(jω)F(jω) Note that the unitygainbandwidth, GB, is GB 0dB log 10 (ω) Phase Shift Uncompensated 40dB/decade /decade /decade Compensated 45 Phase No phase margin Margin 0 log 10 (ω) p 1 p 1 ' p 2 ' p 2 1 GB = A vd (0) p 1 = (g mi g mii R I R II ) g mii R I R II C = g mi c C = g m1 c C = g m2 c Fig. 6.27B ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
24 Introduction to Op Amps (7/17/00) Page 24 Conceptually, where do these roots come from? 1.) The Miller pole: V DD p 1 1 R I (g m6 R II ) R I R II M6 v I g m6 R II Fig V DD V DD 2.) The lefthalf plane output pole: R II RII M6 C II 1 GB C 0 c M6 C II p 2 g m6 C II Fig ) Righthalf plane zero (Zeros always arise from multiple paths from the input to output): V DD R II g m6 R II (1/s ) R II = R II 1/sC v c R II 1/sC v = c where v = v = v. R II g m6 sc 1 c R II 1/sC v c v'' v' M6 Fig ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
25 Introduction to Op Amps (7/17/00) Page 25 Influence of the Mirror Pole Up to this point, we have neglected the influence of the pole, p 3, associated with the current mirror of the input stage. If p 2 p 3, we have problems in compensation. This pole is given approximately as p 3 g m3 C M A vd (0) db F = 1 0 = 0 6dB/octave p 2 Closedloop poles jω p 3 p Openloop poles 1 z 1 σ 0dB Phase Shift Rolloff due to p 3 GB log 10 (ω) 12dB/octave = 0 45 /decade = 0 Phase margin p 1 due to p 3 p 3 p /decade Phase Margin log 10 (ω) Excess Phase due to p 3 Fig A ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
26 Introduction to Op Amps (7/17/00) Page 26 Summary of the Conditions for Stability of the TwoStage Op Amp (Assuming p 3 GB) Unitygainbandwith is given as: GB = A v (0) p 1 = ( ) g mi g mii R I R II 1 g mii R I R II C = g mi c The requirement for 45 phase margin is: ±180 Arg[AF] = ±180 tan1 ω p 1 tan 1 ω p 2 Let ω = GB and assume that z 10GB, therefore we get, ±180 tan1 GB p 1 tan 1 GB p tan 1 (A v (0)) tan 1 GB p tan 1 GB p 2 The requirement for 60 phase margin: p 2 ε 2.2GB if z ε 10GB tan 1 GB z = 45 g m1 g m2 R 1 R 2 1 g m2 R 1 R 2 C = g m1 c = ( ) tan 1 ω z tan 1 (0.1) = 90 tan 1 GB p 2 GB p 2 = p 2 ε 1.22GB = 45 If 60 phase margin is required, then the following relationships apply: 5.7 g m6 > 10g m1 g m6 > 10g m1 and g m6 C 2 > 2.2g m1 > 0.22C 2 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
27 Introduction to Op Amps (7/17/00) Page 27 Controlling the RightHalf Plane Zero Why is the RHP zero a problem? Because it boosts the magnitude but lags the phase the worst possible combination for stability. jω jω 3 jω > θ 1 > θ 2 > θ 3 jω 1 θ1 θ θ3 2 z 1 σ Fig B Solution of the problem: If zeros are caused by two paths to the output, then eliminate one of the paths. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
28 Introduction to Op Amps (7/17/00) Page 28 Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor Model: Inverting HighGain Stage 1 C V c I v OUT V in gmi v in C I R I V out V g mii V R I II C out II The transfer function is given by the following equation, V o (s) V in (s) = (g mi )(g mii )(R I )(R II ) 1 s[r I C I R II C II R I g mii R I R II ] s2[r I R II C II (C I )] Using the technique as before to approximate p 1 and p 2 results in the following and p 1 p R I C I R II C II R I g mii R I R II g mii R I R II g mii C II (C I ) Comments: Poles are approximately what they were before with the zero removed. For 45 phase margin, p 2 must be greater than GB For 60 phase margin, p 2 must be greater than 1.73GB OA047 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
29 Introduction to Op Amps (7/17/00) Page 29 Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero Assume that the unitygain buffer has an output resistance of R o. Model: R o Inverting HighGain Stage 1 C V c I V out v OUT V in gmi v in C I R I R R o o V out g mii V R I II C II OA0475 It can be shown that if the output resistance of the buffer amplifier, R o, is not neglected that another pole occurs at, p 4 and a LHP zero at 1 R o [C I /(C I )] z 2 1 R o Closer examination shows that if a resistor, called a nulling resistor, is placed in series with that the RHP zero can be eliminated or moved to the LHP. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
30 Introduction to Op Amps (7/17/00) Page 30 Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero) Nodal equations: R z Inverting HighGain Stage v OUT V in C I R V z I g mi v in R I g mii V I R II C II V out Fig Solution: g mi V in V I R sc I V I I s (V 1 s R I V out ) = 0 g mii V I V o z R sc II V out II s (V 1 s R out V I ) = 0 z V out (s) V in (s) = a{1 s[(/g mii ) R z ]} 1 bs cs2 ds 3 where a = g mi g mii R I R II b = (C II )R II (C I )R I g mii R I R II R z c = [R I R II (C I C II C I C II ) R z (R I C I R II C II )] d = R I R II R z C I C II William J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of Calif., Santa Barbara, CA. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
31 Introduction to Op Amps (7/17/00) Page 31 Use of Nulling Resistor to Eliminate the RHP Continued If R z is assumed to be less than R I or R II and the poles widely spaced, then the roots of the above transfer function can be approximated as and p 1 p (1 g mii R II )R I g mii R II R I g mii C I C II C I C II g mii C II p 4 = 1 R z C I z 1 = 1 (1/g mii R z ) Note that the zero can be placed anywhere on the real axis. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
32 Introduction to Op Amps (7/17/00) Page 32 Conceptual Illustration of the Nulling Resistor Approach V DD R z R II V out V'' V' M6 Fig The output voltage, V out, can be written as V out = g m6 R II R z 1 sc c R II R z 1 V s R II R II R z 1 s V = when V = V = V. Setting the numerator equal to zero and assuming g m6 = g mii gives, z 1 = 1 (1/g mii R z ) R II g m6 R z g m6 sc 1 c R II R z 1 s V ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
33 Introduction to Op Amps (7/17/00) Page 33 A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p 2 We desire that z 1 = p 2 in terms of the previous notation. Therefore, 1 (1/g mii R z ) = g mii C II The value of R z can be found as jω p 4 p 2 p 1 z 1 σ OA0477 R z = C II C (1/g mii ) c With p 2 canceled, the remaining roots are p 1 and p 4 (the pole due to R z ). For unitygain stability, all that is required is that and p 4 > A v (0) p 1 = (1/R z C I ) > (g mi / ) = GB A v (0) g mii R II R I = g mi Substituting R z into the above inequality and assuming C II >> results in > g mi g mii C I C II This procedure gives excellent stability for a fixed value of C II ( C L ). Unfortunately, as C L changes, p 2 changes and the zero must be readjusted to cancel p 2. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
34 Introduction to Op Amps (7/17/00) Page 34 Increasing the Magnitude of the Output Pole The magnitude of the output pole, p 2, can be increased by introducing gain in the Miller capacitor feedback path. For example, M10 M11 M8 M4 M9 V Bias V DD M7 V 1 r ds8 v OUT Iin R 1 Vs8 R 2 C 2 gm8vs8 g m6 V 1 Ignore r ds8 M6 Iin R 1 V1 1 V s8 R 2 C 2 gm8 g m8 V s8 V g m6 V 1 SS Fig V out V out The resistors R 1 and R 2 are defined as 1 1 R 1 = g ds2 g ds4 g and R 2 = ds9 g ds6 g ds7 where transistors M2 and M4 are the output transistors of the first stage. Nodal equations: I in = G 1 V 1 g m8 V s8 = G 1 V 1 g m8 s g m8 sc V out and 0 = g m6 V 1 g m8 s G 2 sc 2 c g m8 s V out B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of SolidState Circuits, Vol. SC18, No. 6 (Dec. 1983) pp ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
35 Introduction to Op Amps (7/17/00) Page 35 Increasing the Magnitude of the Output Pole Continued Solving for the transfer function V out /I in gives, V out I in = g m6 G 1 G 2 g m8 1 s 1 s g C 2 m8 G 2 G g m6 2 G 1 G s 2 2 C 2 g m8 G 2 Using the approximate method of solving for the roots of the denominator illustrated earlier gives and 1 6 p 1 = g m8 G C 2 2 G g m6 C c g m6 r 2 ds 2 G 1 G 2 p 2 g m6 r ds 2 6 g m8 r 2 ds G 2 C = 2 g m8 G 2 g m6 6 C = g m8 r ds 2 3 p 2 where all the various channel resistance have been assumed to equal r ds and p 2 is the output pole for normal Miller compensation. Result: Dominant pole is approximately the same and the output pole is increased by roughly g m r ds. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
36 Introduction to Op Amps (7/17/00) Page 36 Concept Behind the Increasing of the Magnitude of the Output Pole V DD V DD r ds7 1 GB C 0 M8 c M6 C II g m8 r ds8 3 r ds7 M6 C II Fig R out = r ds7 3 g m6 g m8 r ds8 3 g m6 g m8 r ds8 Therefore, the output pole is approximately, p 2 g m6 g m8 r ds8 3C II ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
37 Introduction to Op Amps (7/17/00) Page 37 FEEDFORWARD COMPENSATION Use two parallel paths to achieve a LHP zero for lead compensation purposes. RHP Zero A LHP Zero A LHP Zero using Follower V i V out V i V out Vi 1 V out Inverting High Gain Amplifier C II R II Inverting High Gain Amplifier C II R II A V i g mii V i C II R II Vout Fig V out (s) V in (s) = A C s g mii /A II s 1/[R II ( C II )] To use the LHP zero for compensation, a compromise must be observed. Placing the zero below GB will lead to boosting of the loop gain which could deteriorate the phase margin. Placing the zero above GB will have less influence on the leading phase caused by the zero. Note that a source follower is a good candidate for the use of feedforward compensation. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
38 Introduction to Op Amps (7/17/00) Page 38 SELFCOMPENSATED OP AMPS Self compensation occurs when the load capacitor is the compensation capacitor (can never be unstable for resistive feedback) db v in R out(must be large) G m R out C L A v (0) db Increasing C L 20dB/dec. OA048 0dB ω Voltage gain: v in = A v (0) = G m R out Dominant pole: 1 p 1 = R out C L Unitygainbandwidth: GB = A v (0) p 1 = G m C L Stability: Large load capacitors simply reduce the GB and the phase is 90 at the unity gain frequency ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
39 Introduction to Op Amps (7/17/00) Page 39 BJT TwoStage Op Amp Circuit: SIMPLE TWOSTAGE OP AMPS V CC DC Conditions: Q8 I 3 I 4 Q6 I Bias Q3 Q4 I 6 I 1 I 2 v OUT Q1 Q2 v IN C L I Q5 7 I 5 Q7 x1 x1 xn V EE OA02 I 5 = I bias, I 1 = I 2 = 0.5I 5 = 0.5I bias, I 7 = I 6 = ni Bias V icm (max) = V CC V EB3 V CE1 (sat) V BE1 V icm (min) = V EE V CE5 (sat) V BE1 V out (max) = V CC V EC6 (sat) V out (min) = V EE V CE7 (sat) Notice that the output stage is class A I sink = I 7 and I source = β F I 5 I 7 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
40 Introduction to Op Amps (7/17/00) Page 40 TwoStage BJT Op Amp Continued Small Signal Performance: Assuming differential mode operation, we can write the smallsignal model as, g m1 v in 2 R 1 C 1 v1 g m2v in 2 g m4 v 1 R 2 C v2 R 3 C 3 2 gm6 v 2 where, R 1 = OA g r π3 r π4 r o3 m3 g R 2 = r π6 r o2 r o4 r π6 and R 3 = r o6 r o7 m3 C 1 = C π3 C π4 s1 s3 C 2 = C π6 s2 s4 and C 3 = C L s6 s7 Note that we have ignored the basecollector capacitors, C µ, except for M6, which is called. Assuming the pole due to C 1 is much greater than the poles due to C 2 and C 3 gives g m1 v in R 2 C 2 v2 R 3 C 3 g m6 v 2 OA04 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
41 Introduction to Op Amps (7/17/00) Page 41 TwoStage BJT Op Amp Continued Summary of the small signal performance: Midband performance A o = g mi g mii R I R II g m1 g m6 r π6 (r o6 r o7 ) = g m1 β F6 (r o6 r o7 ), R out = r o6 r o7, R in = 2r π1 Roots Zero = g mii = g m6 1 1 Poles at p 1 g mii R I R II C = c g m6 r π6 (r o6 r o7 )C = g m1 c A o C and p 2 g mii c C g m6 II C L Assume that β F =100, g m1 = 1mS, g m6 = 10mS, r o6 = r o7 = 0.5MΩ, = 5pF and C L = 10pF: A o = (1mS)(100)( 250kΩ) = 25,000V/V, R in = 2(β F /g m1 ) 2(100kΩ) = 200kΩ, R out = 250kΩ Zero = 10mS 5pF = 2x109 rads/sec or 318.3MHz, p 1 = and 1mS (25,000)5pF = 2x108 25,000 = 8000 rads/sec or 1273Hz, p 2 = 10mS 10pF = 109 rads/sec or MHz 8x103 jω 109 2x109 σ OA06 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
42 Introduction to Op Amps (7/17/00) Page 42 Slew Rate of the TwoStage BJT Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as I lim = C dv C dt where v C is the voltage across the capacitor C. V CC V CC v in >>0 Q3 Q1 VBias I 5 SR = min Q4 Q5 Q2 I 5 V EE Positive Slew Rate I5 Assume a virtural ground Q6 I 6 I CL C L I 7 Q7 v in <<0 Q3 Q1 VBias I 5 Q4 Q5 Q2 V EE Negative Slew Rate I 5 Assume a virtural ground C, I 6 I 5 I 7 c C = I 5 L C because I 6 >>I 5 SR = c min C, I 7 I 5 c C = I 5 L C if I 7 >>I 5. c I 5 Q6 I 6 =0 ICL Therefore, if C L is not too large and if I 7 is significantly greater than I 5, then the slew rate of the twostage op amp should be, SR = I 5 C L I 7 Q7 OA07 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
43 Introduction to Op Amps (7/17/00) Page 43 FoldedCascode BJT Op Amp Circuit V Bias Q3 I C3 V CC i C10 Q10 Q11 i C11 V BE V CE (sat) V CC i C10 Q10 Q11 i C11 v in i C1 Q1 Q2 Q8 i C2 V Bias Q6 Q7 Q9 i out Q8 Q6 Q9 Q7 i out R A RB V Bias Q4 I C4 Q5 V EE Simplified circuit I C5 V BE V CE (sat) V BE Q4 I C4 Q5 I C5 V EE Biasing details of the output DC Conditions: I 3 = I bias, I 1 = I 2 = 0.5I 5 = 0.5I bias, I 4 = I 5 = ki Bias I 10 = I 11 = ki Bias 0.5I bias (k>1) V icm (max) = V CC V CE3 (sat) V EB1 V icm (min) = V EE V CE4 (sat) V EC1 (sat) V BE1 OA08 V out (max) = V CC V EC9 (sat) V EC11 (sat) V out (min) = V EE V CE5 (sat) V CE7 (sat) Notice that the output stage is pushpull I sink and I source are limited by the base current. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
44 Introduction to Op Amps (7/17/00) Page 44 FoldedCascode BJT Op Amp Continued SmallSignal Analysis: R A g m6 v be6 g m1 v in 2 r r π6 r o6 o1 r v be6 o4 1 g m10 where R A 1/g m6 and R B r o7 β P r o11 /2 1g m7 r o7 r π7 2 if r o7 r o11 R B g m7 v be7 i 10 g m2 v in v r o7 2 be7 r o2 r o5 r π7 i 10 i 7 βr o11 OA09 i 10 g m1 r π6 v in 2(r π6 R A ) g m1 v in 2 i 7 g m2 r π7 v in 2(r π7 R B ) g m2 r π7 v in 2(r π7 0.5r π7 ) = g m2 v in 3 = (i 7 i 10 )β P R out v in = 5 6 (g m1 β P R out )v in if g m1 = g m2 v in = 5 6 (g m1 β P R out ) R out = β P r o11 [β Ν (r o5 r o2 )] and R in = 2r π1 Assume that β FN =100, β FP =50, g m1 = g m2 =1mS, r on = 1MΩ, and r op = 0. 5MΩ: v in = 14,285V/V R out = MΩ and R in = 100kΩ ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
45 Introduction to Op Amps (7/17/00) Page 45 FoldedCascode BJT Op Amp Continued Frequency response includes only 1 dominant pole at the output (selfcompensation), 1 p 1 = R out C L There are other poles but we shall assume that they are less than GB If C L = 25pF, then p 1 = 2800 rads/sec. or 446Hz Checking some of the nondominant poles gives: p A = p B = GB = MHz 1 R A C A = g m6 C A 159MHz if C A = 1pf (the capacitance to ac ground at the emitter of Q6) 1 2 R B C = B r π7 C 6.37MHz if C B = 1pf (the capacitance to ac ground at the emitter of Q7) B This indicates that for small capacitive loads, this op amp will suffer from higher poles with respect to phase margin. Capacitive loads greater than 25pF, will have better stability (and less GB). ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
46 Introduction to Op Amps (7/17/00) Page 46 TwoStage CMOS Op Amp Circuit: DC Conditions: M8 I Bias I 3 I 1 V DD V SG4 V SG6 M3 M4 M6 I 4 I 6 I 42 M1 M2 C L v in I 7 I 5 M7 M5 x1 x1 xn V SS OA10 I 5 = I bias, I 1 = I 2 = 0.5I 5 = 0.5I bias, I 7 = I 6 = ni Bias V icm (max) = V DD V SG3 V T1 V icm (min) = V SS V DS5 (sat) V GS1 V out (max) = V DD V SD6 (sat) V out (min) = V SS V DS7 (sat) Notice that the output stage is class A I sink = I 7 and I source = K N W 6 2L 6 (V DD V SS V T ) 2 I 7 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
47 Introduction to Op Amps (7/17/00) Page 47 DC Balance Conditions for the TwoStage Op Amp For best performance, keep all transistors in saturation. M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages. Therefore, we develop conditions to force M4 to be in saturation. 1.) First assume that V SG4 = V SG6. This will cause proper mirroring in the M3M4 mirror. Also, the gate and drain of M4 are at the same potential so that M4 is guaranteed to be in saturation. S 6 2.) Let S i W i L, if V SG4 = V SG6, then I 6 = i S I 4 4 M3 V SG4 M4 V DD I 4 M1 M2 v in I 5 VBias M5 V SS V SG6 M6 I 6 C L I 7 M7 Fig. 6.31A 3.) However, I 7 = S 7 S I 5 = 5 S 7 S 5 ( 2I 4 ) 4.) For balance, I 6 must equal I 7 S 6 S 4 = 2S 7 S 5 which is called the balance conditions 5.) So if the balance conditions are satisfied, then V DG4 = 0 and M4 is saturated. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
48 Introduction to Op Amps (7/17/00) Page 48 SmallSignal Performance of the TwoStage CMOS Op Amp M8 V DD V SG4 V SG6 I Bias I 3 M3 M4 I 4 I 1 I 42 M6 M1 M2 v in I 7 I 5 M7 M5 x1 x1 xn V SS I 6 C L v 1 v2 g m1 v in 2 1 g m1 v in r ds1 r ds3 C M g m3 2 g m4 v 1 g m3 > g ds2 g ds4 C 1 rds2 r ds4 g m6 v 2 r ds6 r ds7 C L g m3 C M > GB v in v 2 g m1 v in CI rds2 r ds4 g m6 v C 2 II rds6 r ds7 OA11 SmallSignal Performance of the TwoStage CMOS Op Amp Summary of the small signal performance: ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
49 Introduction to Op Amps (7/17/00) Page 49 Midband performance A o = g mi g mii R I R II g m1 g m6 (r ds2 r ds4 )(r ds6 r ds7 ), R out = r ds6 r ds7, R in = Roots Zero = g mii = g m6 1 Poles at p 1 g mii R I R II C = (g ds2 g ds4 )(g ds6 g ds7 ) c g m6 C and p 2 g mii c C g m6 II C L Assume that g m1 = 100µS, g m6 = 1mS, r ds2 = r ds4 = 2MΩ r ds6 = r ds7 = 0.5MΩ, = 5pF and C L = 10pF: A o = (100µS)(1MΩ)(1000µS)(0.25MΩ) = 25,000V/V, R in =, R out = 250kΩ Zero = 1000µS 5pF p 1 = and = 2x108 rads/sec or 31.83MHz, 1 (1mS)(1MΩ)(0.25MΩ)(5pF) = 800 rads/sec or 127.3Hz, GB = 3.178MHz p 2 = 1000µS 10pF = 108 rads/sec or MHz 8x102 jω 108 2x108 σ OA12 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
50 Introduction to Op Amps (7/17/00) Page 50 Slew Rate of a TwoStage CMOS Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as I lim = C dv C dt where v C is the voltage across the capacitor C. V DD V DD v in >>0 M3 M1 VBias I 5 SR = min M4 M2 M5 I 5 V SS Positive Slew Rate I5 Assume a virtural ground M6 I 6 I CL C L I 7 M7 v in <<0 M3 M1 VBias I 5 M4 M2 M5 V SS I 5 Assume a virtural ground M6 I 6 =0 ICL C L I 7 M7 Negative Slew Rate Fig C, I 6 I 5 I 7 c C = I 5 L C because I 6 >>I 5 SR = c min C, I 7 I 5 c C = I 5 L C if I 7 >>I 5. c Therefore, if C L is not too large and if I 7 is significantly greater than I 5, then the slew rate of the twostage op amp should be, SR = I 5 Folded Cascode, CMOS Op Amp I 5 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
51 Introduction to Op Amps (7/17/00) Page 51 V DD M14 M4 I 4 M5 I 5 A B R A R B I 1 I 2 v in M1 M2 R 1 M13 M6 R 2 I 6 M7 I7 C L VBias I 3 M3 V SS M8 M12 M10 M9 M11 Fig Comments: The bias currents, I 4 and I 5, should be designed so that I 6 and I 7 never become zero (i.e. I 5 =I 6 =1.5I 3 ) This amplifier is nearly balanced (would be exactly if R A was equal to R B ) Self compensating Poor noise performance, the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors. (Some first stage gain can be achieved if R A and R B are greater than g m1 or g m2. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
52 Introduction to Op Amps (7/17/00) Page 52 SmallSignal Analysis of the Folded Cascode Op Amp Model: R A g m6 v gs6 g m1 v in r 2 r ds1 r v gs6 ds6 ds4 R 2 1 g m10 R B g m7 v gs7 i 10 g m2 v in r 2 r ds2 r v gs7 ds7 ds5 Recalling what we learned about the resistance looking into the source of the cascode transistor, R A = r ds6 R 2 (1/g m10 ) 1 g m6 r gs6 1 g m6 and R B = r ds7 R II R II 1 g m7 r ds7 g m7 r where R II g m9 r ds9 r ds11 ds7 The smallsignal voltage transfer function can be found as follows. The current i 10 is written as i 10 = g m1 (r ds1 r ds4 )v in 2[R A (r ds1 r ds4 )] g m1 v in 2 and the current i 7 can be expressed as i 7 = g m2 (r ds2 r ds5 )v in 2 R II g m7 r (r ds2 r ds5 ) ds7 = g m2 v in g m2 v in 2 1 R II (g ds2 g ds5 ) = 2(1k) g m7 r ds7 The output voltage,, is equal to the sum of i 7 and i 10 flowing through R out. Thus, v in = g m1 2 g m2 2(1k) R out = 2k 22k g mi R out i 10 i 7 R II Fig where k = R II (g ds2 g ds4 ) g m7 r ds7 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
53 Introduction to Op Amps (7/17/00) Page 53 Frequency Response of the Folded Cascode Op Amp The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as 1 p out = R out C out where C out is all the capacitance connected from the output of the op amp to ground. All other poles must be greater than GB = g m1 /C out. The approximate expressions for each pole is 1.) Pole at node A: 1 p A R A C A 2.) Pole at node B: 1 p B R B C B 3.) Pole at drain of M6: 1 p 6 (R 2 1/g m10 )C 6 4.) Pole at source of M8: p 8 g m8 C 8 5.) Pole at source of M9: p 9 g m9 C 9 6.) Pole at gate of M10: p 10 g m10 C 10 where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance seen to ground from a given node. One might feel that because R B is approximately r ds that this pole might be too small. However, at frequencies where this pole has influence, C out, causes R out to be much smaller making p B also nondominant. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
54 Introduction to Op Amps (7/17/00) Page 54 Folded Cascode, CMOS Op Amp Example Assume that all g mn = g mp = 100µS, r dsn = 2MΩ, r dsp = 1MΩ, and C L = 10pF. Find all of the smallsignal performance values for the foldedcascode op amp. R II = 0.4GΩ, R A = 10kΩ, and R B = 4MΩ k = 0.4x109 (0.3x10 6 ) 100 = 1.2 v = 21.2 in 22.2 (100)(57.143) = 4,354V/V R out = R II [g m7 r ds7 (r ds5 r ds2 )] = 400MΩ [(100)(0.667MΩ)] = MΩ 1 1 p out = R out C = = 1,750 rads/sec. 278Hz GB = 1.21MHz out MΩ 10pF Comments on the Folded Cascode, CMOS Op Amp: Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance (use Miller compensation in this case) Need first stage gain for good noise performance Widely used in telecommunication circuits where large dynamic range is required ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
55 Introduction to Op Amps (7/17/00) Page 55 Unbuffered, TwoStage CMOS Op Amp OP AMP DESIGN V DD M3 M4 M6 M1 M2 v in VBias M5 V SS M7 C L Fig Notation: S i = W i L i = W/L of the ith transistor ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
56 Introduction to Op Amps (7/17/00) Page 56 Design Relationships for the TwoStage Op Amp Slew rate SR = I 5 (Assuming I 7 >>I 5 and C L > ) Firststage gain A v1 = Secondstage gain A v2 = Gainbandwidth GB = g m1 Output pole p 2 = g m6 C L g m1 g ds2 g ds4 = 2g m1 I 5 (λ 2 λ 4 ) g m6 g m6 = g ds6 g ds7 I 6 (λ 6 λ 7 ) RHP zero z 1 = g m6 60 phase margin requires that g m6 = 2.2g m2 (C L / ) if all other roots are 10GB. Positive ICMR V in(max) = V DD Negative ICMR V in(min) = V SS I 5 β 3 V T03 (max) V T1(min) ) I 5 β 1 V T1(max) V DS5 (sat) 2I DS Saturation voltagev DS (sat) = β It is assumed that all transistors are in saturation for the above relationships. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
57 Introduction to Op Amps (7/17/00) Page 57 Op Amp Specifications The following design procedure assumes that specifications for the following parameters are given. 1. Gain at dc, A v (0) 2. Gainbandwidth, GB 3. Phase margin (or settling time) 4. Input commonmode range, ICMR 5. Load Capacitance, C L 6. Slewrate, SR 7. Output voltage swing 8. Power dissipation, P diss M3 M4 v in M1 M2 VBias Max. ICMR and/or p 3 V SG4 GB = g m1 M5 V DD V SS V SG6 0.2C L (PM = 60 ) M7 V out (max) M6 I 6 g m6 or Proper Mirroring V SG4 =V SG6 C L Min. ICMR I 5 I5 = SR V out (min) Fig ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
58 Introduction to Op Amps (7/17/00) Page 58 Unbuffered Op Amp Design Procedure This design procedure assumes that the gain at dc (A v ), unity gain bandwidth (GB), input common mode range (V in (min) and V in (max)), load capacitance (C L ), slew rate (SR), settling time (T s ), output voltage swing (V out (max) and V out (min)), and power dissipation (P diss ) are given. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors. 1. From the desired phase margin, choose the minimum value for, i.e. for a 60 phase margin we use the following relationship. This assumes that z 10GB. > 0.22C L 2. Determine the minimum value for the tail current (I 5 ) from the largest of the two values. I 5 = SR. Cc or I 5 10 V DD V SS 2. Ts 3. Design for S 3 from the maximum input voltage specification. I 5 S 3 = K' 3 [V DD V in (max) V T03 (max) V 1 T1 (min)]2 4. Verify that the pole of M3 due to C gs3 and C gs4 (=0.67W 3 L 3 C ox ) will not be dominant by assuming it to be greater than 10 GB g m3 2C gs3 > 10GB. 5. Design for S 1 (S 2 ) to achieve the desired GB. g m1 = GB. S 2 = g m2 K' 2 I 5 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
59 Introduction to Op Amps (7/17/00) Page 59 Unbuffered Op Amp Design Procedure Continued 6. Design for S 5 from the minimum input voltage. First calculate V DS5 (sat) then find S 5. V DS5 (sat) = V in (min) V SS I 5 2I 5 V β T1 (max) 100 mv S 5 = 1 K' 5 [V DS5 (sat)]2 7. Find S 6 by letting the second pole (p 2 ) be equal to 2.2 times GB and assuming that V SG4 = V SG6. g m6 = 2.2g m2 (C L / ) S 6 = S 4 g m6 g m4 8. Calculate I 6 from I 6 = g m6 2 2K' 6 S 6 Check to make sure that S 6 satisfies the V out (max) requirement and adjust as necessary. 9. Design S 7 to achieve the desired current ratios between I 5 and I 6. S 7 = (I 6 /I 5 )S 5 (Check the minimum output voltage requirements) 10. Check gain and power dissipation specifications. 2g m2 g m6 A v = P I 5 (λ 2 λ 3 )I 6 (λ 6 λ 7 ) diss = (I 5 I 6 )(V DD V SS ) 11. If the gain specification is not met, then the currents, I 5 and I 6, can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the power dissipation is too high, then one can only reduce the currents I 5 and I 6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. 12. Simulate the circuit to check to see that all specifications are met. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
60 Introduction to Op Amps (7/17/00) Page 60 Example 6.31 Design of a TwoStage Op Amp Using the material and device parameters given in Tables 3.11 and 3.12, design an amplifier similar to that shown in Fig that meets the following specifications. Assume the channel length is to be 1µm. A v > 3000V/V V DD = 2.5V V SS = 2.5V 60 phase margin GB = 5MHz C L = 10pF SR > 10V/µs V out range = ±2V ICMR = 1 to 2V P diss 2mW Solution 1.) The first step is to calculate the minimum value of the compensation capacitor, which is > (2.2/10)(10 pf) = 2.2 pf 2.) Choose as 3pF. Using the slewrate specification and calculate I 5. I 5 = (3x10 12 )( ) = 30 µa 3.) Next calculate (W/L) 3 using ICMR requirements (W/L) 3 = 6 (50x10 6 )[ ] 2 = 3 (W/L) 3 = (W/L) 4 = 3 4.) Now we can check the value of the mirror pole, p 3, to make sure that it is in fact greater than 10GB. Assume the C ox = 0.4fF/µm 2. The mirror pole can be found as p 3 g m3 2K p S 3 I 3 2C = gs3 2(0.667)W 3 L 3 C = 6.79x10 9 (rads/sec) ox or 1.08 GHz. Thus, p 3, is not of concern in this design because p 3 >> 10GB. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
61 Introduction to Op Amps (7/17/00) Page 61 Example 6.31 Continued 5.) The next step in the design is to calculate g m1 to get Therefore, (W/L) 1 is 6.) Next calculate V DS5, g m1 = (5x10 6 )(2π)(3x10 12 ) = 94.25µS (W/L) 1 = (W/L) 2 = g m1 2 2K N I 1 = (94.25) = (W/L) 1 = (W/L) 2 = 3 30x10 V DS5 = ( 1) ( 2.5) 6.85 = 0.35V 110x106 3 Using V DS5 calculate (W/L) 5 from the saturation relationship. 2(30 106) (W/L) 5 = ( )(0.35)2 = (W/L) 5 = ) For 60 phase margin, we know that g m6 10g m µS Assuming that g m6 = 942.5µS and knowing that g m4 = 67µS, we calculate (W/L) 6 as (W/L) 6 = (67 106) = ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
62 Introduction to Op Amps (7/17/00) Page 62 Example 6.31 Continued ( )2 8.) Calculate I 6 using the smallsignal g m expression: I 6 = = 211.5µA 212µA (2)(50 106)(42) If we calculate (W/L) 6 based on V out (max), the value is approximately 38. Since 42 exceeds the specification and maintains better phase margin, we will stay with (W/L) 6 = 42 and I 6 = 212µA. With I 6 = 212µA the power dissipation is P diss = 5V (30µA212µA) = 1.21mW. 9.) Finally, calculate (W/L) 7 (W/L) 7 = = (W/L) 7 = 35 Let us check the V out (min) specification although the W/L of M7 is so large that this is probably not necessary. The value of V out (min) is V out (min) = V DS7 (sat) = = 0.349V which is less than required. At this point, the firstcut design is complete. 10.) Now check to see that the gain specification has been met A v = ( )( ) (.04.05) (.04.05) = 3,383V/V which barely meets specifications. We might want to consider decreasing the output current back to 190µA to increase the secondstage gain by a factor of 1.1 or better yet, increase the channel length to 2µm causing a gain increase of 20. ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
63 Introduction to Op Amps (7/17/00) Page 63 Incorporating the Nulling Resistor into the Miller Compensated TwoStage Op Amp Circuit: V DD M11 V A M10 M3 C M M4 V B M8 M6 vout V C v in M1 M2 v in C L I Bias M12 M9 M5 M7 V SS Fig We saw earlier that the roots were: p 1 = g m2 A v = g m1 A v p 2 = g m6 C L 1 1 p 3 = R z C z 1 = I R z /g m6 where A v = g m1 g m6 R I R II. (Note that p 3 is the pole resulting from the nulling resistor compensation technique.) ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
64 Introduction to Op Amps (7/17/00) Page 64 Design of the Nulling Resistor (M8) In order to place the zero on top of the second pole (p 2 ), the following relationship must hold R z = 1 g m6 C L C C c C L 1 = c 2K P S 6 I 6 The resistor, R z, is realized by the transistor M8 which is operating in the active region because the dc current through it is zero. Therefore, R z, can be written as v DS8 R z = i D8 V DS8 =0 = 1 K P S 8 (V SG8 V TP ) The bias circuit is designed so that voltage V A is equal to V B. V GS10 V T = V GS8 V T V SG11 = V SG6 In the saturation region V GS10 V T = 2(I 10 ) K' P (W 10 /L 10 ) = V GS8 V T W 11 L 11 = I 10 W 6 I 6 L 6 1 K P S 10 R z = K P S 8 2I = 1 S S 8 2K P I 10 Equating the two expressions for R z gives W 8 L = 8 S 10 S 6 I 6 C L I 10 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
65 Introduction to Op Amps (7/17/00) Page 65 Example 6.32 RHP Zero Compensation Use results of Ex and design compensation circuitry so that the RHP zero is moved from the RHP to the LHP and placed on top of the output pole p 2. Use device data given in Ex Solution The task at hand is the design of transistors M8, M9, M10, M11, and bias current I 10. The first step in this design is to establish the bias components. In order to set V A equal to V B, thenv SG10 must equal V SG6. Therefore, S 11 = (I 11 /I 6 )S 6 Choose I 11 = I 10 = I 9 = 30µA which gives S 11 = (30A/212µA)42 = W 11 = 6µm The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1. There must be sufficient supply voltage to support the sum of V SG11, V SG10, and V DS9. The ratio of I 10 /I 5 determines the (W/L) of M9. This ratio is (W/L) 9 = (I 10 /I 5 )(W/L) 5 = (30/30)(4.5) = 4.5 W 9 = 4.5µm Now (W/L) 8 is determined to be (W/L) 8 = 3pF 3pF10pF µA 30µA W 8 = 3.98µm 4µm = 3.98 ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
66 Introduction to Op Amps (7/17/00) Page 66 Example 6.32 Continued It is worthwhile to check that the RHP zero has been moved on top of p 2. To do this, first calculate the value of R z. V SG8 must first be determined. It is equal to V SG10, which is V SG10 = Next determine R z. 2I 10 K P S 10 V TP = = 1.795V R z = The location of z 1 is calculated as The output pole, p 2, is 1 K P S 8 (V SG10 V TP ) = ( ) = 4.601kΩ 1 z 1 = ( )(3x x10 ) 12 = 94.16x106 rads/sec 942.5x10 6 p 2 = 942.5x106 10x10 12 = 94.25x106 rads/sec Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved from the RHP to the LHP. The results of this design are summarized below. W 8 = 4µm W 9 = 4.5µm W 10 = 1µm W 11 = 6µm ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
67 Introduction to Op Amps (7/17/00) Page 67 An Alternate Form of Nulling Resistor To cancel p 2, V DD z 1 = p 2 R z = C L 1 g m6a C = C g m6b Which gives g m6b = g m6a C L In the previous example, g m6a = 942.5µS, = 3pF and C L = 10pF. M1 M2 v in VBias M3 M4 M5 M11 M6B M8 V SS M10 M9 M6 M7 C L Fig. 6.34A Choose I 6B = 10µA to get g m6b = g m6a C L 2K P W 6B I 6B L = 6B C c C L 2K P W 6A I D6 L 6A or W 6B L 6B = I 6A W 6A I 6B L = 6A (23) = 28.7 W 6B = 29µm ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
68 Introduction to Op Amps (7/17/00) Page 68 Implementation of using a MOS Transistor Two Approaches: 1.) Have to keep V GS V T C GB C GS V SS V GS 2.) Better V GS not restricted V T V GS Fig B C GS C GB V GS V T V GS Fig. 6.34C ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
69 Introduction to Op Amps (7/17/00) Page 69 Programmability of the TwoStage Op Amp The following relationships depend on the bias current, I bias, in the following manner and allow for programmability after fabrication. 1 A v (0) = g mi g mii R I R II I Bias M3 V DD M4 M6 GB = g mi I Bias P diss = (V DD V SS )(1K 1 K 2 )I Bias I bias SR = K 1 I Bias I Bias R out = p 1 = 1 1 2λK 2 I Bias I Bias 1 g mii R I R II C I Bias 2 I 1.5 c I Bias Bias z = g mii I Bias Illustration of the I bias dependence P diss and SR p 1 GB and z Ao and R out M1 M2 v in IBias K 1 IBias K 2IBias M5 M7 V SS Fig D I Bias I Bias (ref) Fig. 6.34E ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
70 Introduction to Op Amps (7/17/00) Page 70 Simulation of the Electrical Design Area of source or drain = AS = AD = W[L1 L2 L3] where L1 = Minimum allowable distance between the contact in the S/D and the polysilicon (5µm) L2 = Width of a minimum size contact (5µm) L3 = Minimum allowable distance from the contact in S/D to the edge of the S/D (5µm) AS = AD = Wx15µm Perimeter of the source or drain = PD = PS = 2W 2(L1L2L3) PD = PS = 2W 30µm Illustration: L3 L2 L1 L1 L2 L3 Poly W Diffusion Diffusion L Fig ECE 4430 Analog Integrated Circuits and Systems P.E. Allen, 2000
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