V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

Size: px
Start display at page:

Download "V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs"

Transcription

1 ECE 642, Spring Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant pole of 0 5 radians/sec., a slew rate of 5V/µs an output swing of V. (a.) If V in = mv find the propagation delay time of this comparator (the time for the output to go halfway from one state to the other). (b.) Repeat part (a.) if V in = 0mV. (c.) Repeat part (a.) if V in = 00mV. a.) We know that the linear output voltage of a single-pole comparator can be written as, v out (t) = A(-e -tp )V in which can be solved for the propagation delay time as t p = τ ln 2k 2k- where k = V in V in (min) V in (min) = (V OH -V OL ) A = V 0 4 = 0.mV We must first determine if the comparator is linear or slewing. The maximum slope occurs at t = 0 is given as dv out (t) dt = A p V in e -tp _ The comparator is not slewing t p is given as t p = τ ln 2k 2k- = 0-5 ln = 0.53µs dv out (0) dt = A p V in = = 0 6 = V/µs b.) We see the maximum slope for the linear response is 0V/µs which means that the comparator is slewing. Slewing at a rate of 5V/µs requires 0.µs to go 0.5V. Therefore, t p = 0.00µs c.) The answer is the same as b.) namely t p = 0.00µs

2 ECE 642, Spring Final Exam Page 2 Problem 2 - (20 points - This problem is optional) Assume the capacitors connected to the drains of M M2 (C C 2 ) are initially discharged. Express V out = v o2 v o as a function of the applied input, V in = v i -v i2, in the M3 M4 v o v o2 time domain assuming V in is a step input. If g m = g m2 = ms, g m3 = g m4 = 00µS, C = C 2 = pf, what is the v i v i2 M M2 propagation delay time ( V out = 0.5(V OH V OL ) ) for a step input of V in = 0.0( V OH V OL )? I BIAS Small-signal model: S03FEP2 v o C v o2 C g m v gs r ds r ds3 - g m3 v gs3 g m2 v gs2 r ds2 r ds4 - g m4 v gs4 S03FES2 The nodal equations corresponding two these two circuits are: g m v gs g ds v o g d3 v o sc v o g m3 v gs3 = 0 g m2 v gs2 g ds2 v o2 g d4 v o2 sc 2 v o2 g m4 v gs4 = 0 We can write that, (g ds g ds3 sc ) v o = - g m v gs g m3 v gs3 (g ds2 g ds4 sc 2 ) v o2 = - g m v gs2 g m4 v gs4 Assuming matching, we get (v o2 v o )(g ds g ds3 sc ) = g m (v gs - v gs2 ) g m3 (v gs3 - v gs4 ) or (v o2 v o )(g ds g ds3 sc ) = g m (v i - v i2 ) g m3 (v o2 v o ) (v o2 v o )(g ds g ds3 sc - g m3 ) (v o2 v o )( sc - g m3 ) = g m (v i - v i2 ) g m (v o2 v o ) = V out (s) = sc - g V m3 in (s) = g m g m3 g m3 /C s - (g v in m3 /C ) s V out (s) = g m C v in k s k 2 s- (g = g m m3 /C ) g m3 g m3 /C s - (g v in m3 /C ) s Solving for k k 2 gives k = -(C /g m3 ) k 2 = (C /g m3 ). Thus, V out (s) = g m g m3 s - (g m3 /C ) - s in If V in = 0.0( V OH V OL ), then v out (t) = g m g m3 V in [e (g m3/c )t ] or 0.5(V OH V OL ) = 0.(V OH V OL )[e 08 t p -] 5 = e 08 t p - e 08 t p = 6 t p = ln(6) = 0 8 = 9.92 ns

3 ECE 642, Spring Final Exam Page 3 Problem 3 - (20 points - This problem is optional) An internally-compensated, cascode op amp is shown. (a) Derive an expression for the common-mode input range. (b) Find W /L, W 2 /L 2, W 5 /L 5, W 6 /L 6 when I BIAS is 80 A the input CMR is -.25 V to 2 V. Use K' N = 0 A/V 2, K' p = 50 A/V 2 V T = 0.6 to 0.8V. (c.) Develop an expression for the small-signal differential-voltage gain output resistance of the cascode op amp. 40/ M2 M0 M I Bias - v in M3 M = 2.5V M6 M4 I 7 M2 M7 0/ V SS = -2.5V M4 M3 C c M8 M9 C L S03FEP3 (a.) (min) = V SS V DS7 (sat) V DS (sat) V T (max) (max) = - V SD5 (sat) - V T5 (max) V T (min) (we will ignore that M8 M4 cause a more severe upper ICM limit) ICMR = (max) - (min) ICMR = ( V SS )[V DS7 (sat)v DS (sat)v T (max)] [V SD5 (sat)v T5 (max)-v T (min)] (b.) I 7 = 4 I BIAS = 20 A Using V DS (sat) = 2I K (W/L) W L = 2I K [V DS (sat)] 2gives, V DS7 (sat) = 0.9V (min) = -2.5V0.9VV DS (sat)0.8v V DS (sat) = 0.259V W = W 2 20 A = L L 2 0Æ0.2592= 2.70 (max) = 2.0V = 2.5V - V SD5 (sat) - 0.6V 0.8V V SD5 (sat) = 0.3V W 5 = W 6 = 20 A L 5 L 6 50Æ0.32= 4.44 (c.) By inspection, we can write: g m4 A v = (-g m r ds2 ) g m4 g ds3 g ds4 -g m8 g ds8 g ds9 v out

4 ECE 642, Spring Final Exam Page 4 Problem 4 - (20 points - This problem is optional) George P. Burdell has submitted the following input stage for the design challenge problem in ECE 642. Assuming that the transistor model parameters are K N =0µA/V 2, V TN = 0.7V, λ N =0.04V -, K P =/V 2, V TP = -0.7V, λ P =0.05V -, your job is to check this op amp out. In particular, what is the upper lower input common mode voltages, what is the minimum power supply that gives zero input common mode range, what is the smallsignal voltage gain, compare this input stage with the classical differential input stage (list advantages disadvantages). M3 22 M4 00µA 00µA M3 22 M Vout - M Vout - M M6 00 M7 M M2 M9 00 M8 M M V i 0 0 V i - V i V i - 5µA 0 M0 0 5µA 0 M0 0 S03FEP4 The George P. Burdell Approach GPB Differential Input Stage: Classical Approach = V SD3 (sat) V T - V GS6 (50 A) = V SD3 (sat) V T V GS6 (sat) V T6 V icm = V SD3 (sat) V GS6 (sat) V - icm = V DS5 (sat) V GS (50 A) - V GS6 (50 A) = V DS5 (sat) V DS (sat) - V DS6 (sat) V DS (sat) = V DS6 (sat) = 2Æ50 0Æ0 = 0.30V, V DS5 (sat) = 2Æ00 0Æ0 = 0.426V, 2Æ50 V SD3 (sat) = 50Æ22 = 0.30V V icm = 0.602V - = = 0.426V Note that V DS6 = V GS6 -V GS7 = = 0.27 < V DS6 (sat) so that M6 is slightly in the active region but this is not a problem. The minimum is found by letting V icm = V - icm which gives (min) =.028V V out The small-signal voltage gain is A vd = V i - V - = -g m -g m2 = i g ds g ds3 g ds2 g ds4 Classical Differential Input Stage: = V SD3 (sat) V T = = 0.4V - = V DS5 (sat) V GS (50 A) =.427V (min) =.027V the small-signal voltage gain is the same.

5 ECE 642, Spring Final Exam Page 5 Problem 4 Continued Comparison between the two approaches: Characteristic GBP Differential Amplifier Classical Differential Amplifier V icm 0.602V 0.4V V - icm 0.426V.427V (min).028v.027v P diss (360 A) (250 A) Noise Higher Lower Input Offset Voltage Larger Smaller Small-signal gain Same Same Useable ICMR Within power supply Outside of power supply

ECE 6412, Spring Final Exam Page 1

ECE 6412, Spring Final Exam Page 1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

More information

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

More information

Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 140 Simple Op Amps (2/11/02) Page 140-1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

More information

PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION

PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION Practice Problems (5/27/07) Page PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION TECHNOLOGY Problem (044430E3P5) The following questions pertain to a standard npn BJT process. a.) Give the

More information

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog

More information

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 = ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.

More information

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1 Lecture 50 Simple BJT Op Amps (/28/04) Page 50 LECTURE 50 SIMPLE BJT OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace

More information

Lecture 37: Frequency response. Context

Lecture 37: Frequency response. Context EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

6.2 INTRODUCTION TO OP AMPS

6.2 INTRODUCTION TO OP AMPS Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1 Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators

More information

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5. Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232-242 Two-stage op-amp Analysis Strategy Recognize

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

More information

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130 ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED

More information

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E.

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E. Lecture 070 Stage Frequency esponse I (/0/0) Page 070 LECTUE 070 SINGLESTAGE FEQUENCY ESPONSE I (EADING: GHLM 488504) Objective The objective of this presentation is:.) Illustrate the frequency analysis

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

More information

Lecture 06: Current Mirrors

Lecture 06: Current Mirrors Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26 Lowered Resistance Looking into

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web:     Ph: Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 0-4546 CLASS TEST 08-9 ELECTCAL ENGNEENG Subject

More information

EXAMPLE DESIGN PART 2

EXAMPLE DESIGN PART 2 ECE37 Advanced Analog Circuits Lecture 4 EXAMPLE DESIGN PART 2 Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS analog

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

ECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 1-19 in the exam: please make sure all are there.

ECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 1-19 in the exam: please make sure all are there. ECE37B Final Exam There are 5 problems on this exam and you have 3 hours There are pages -9 in the exam: please make sure all are there. Do not open this exam until told to do so Show all work: Credit

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

More information

Sample-and-Holds David Johns and Ken Martin University of Toronto

Sample-and-Holds David Johns and Ken Martin University of Toronto Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

ECEN 325 Electronics

ECEN 325 Electronics ECEN 325 Electronics Operational Amplifiers Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering Opamp Terminals positive supply inverting input terminal non

More information

4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP)

4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP) emp. Indep. Biasing (7/14/00) Page 1 4.5 (A4.3) - EMPERAURE INDEPENDEN BIASING (BANDGAP) INRODUCION Objective he objective of this presentation is: 1.) Introduce the concept of a bandgap reference 2.)

More information

MC MC35172 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS.. GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2.1MHz, 2V/µs

MC MC35172 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS.. GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2.1MHz, 2V/µs MC3372 MC3572 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2MHz, 2/µs SINGLE (OR DUAL) SUPPLY OPERATION FROM +4 TO +44 (±2 TO ±22) WIDE INPUT COMMON MODE

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 2

55:041 Electronic Circuits The University of Iowa Fall Exam 2 Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

Switching circuits: basics and switching speed

Switching circuits: basics and switching speed ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

8 sin 3 V. For the circuit given, determine the voltage v for all time t. Assume that no energy is stored in the circuit before t = 0.

8 sin 3 V. For the circuit given, determine the voltage v for all time t. Assume that no energy is stored in the circuit before t = 0. For the circuit given, determine the voltage v for all time t. Assume that no energy is stored in the circuit before t = 0. Spring 2015, Exam #5, Problem #1 4t Answer: e tut 8 sin 3 V 1 For the circuit

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OVA & OTA 1 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly

More information

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

More information

EXAMPLE DESIGN PART 2

EXAMPLE DESIGN PART 2 ECE37 Advanced Analog Circuits Lecture 3 EXAMPLE DESIGN PART 2 Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS analog

More information

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM 425434 and 624638, AH 249260) INTRODUCTION The objective of this presentation is to present the

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

More information

ECE137B Final Exam. Wednesday 6/8/2016, 7:30-10:30PM.

ECE137B Final Exam. Wednesday 6/8/2016, 7:30-10:30PM. ECE137B Final Exam Wednesday 6/8/2016, 7:30-10:30PM. There are7 problems on this exam and you have 3 hours There are pages 1-32 in the exam: please make sure all are there. Do not open this exam until

More information

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm-1 Exam (Solution)

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm-1 Exam (Solution) Georgia Institute of Technology School of Electrical and Computer Engineering Midterm-1 Exam (Solution) ECE-6414 Spring 2012 Friday, Feb. 17, 2012 Duration: 50min First name Solutions Last name Solutions

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

Lectures on STABILITY

Lectures on STABILITY University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science νin ( ) Effect of Feedback on Frequency Response a SB Robert W. Brodersen EECS40 Analog

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

Electronics II. Final Examination

Electronics II. Final Examination The University of Toledo f6fs_elct7.fm - Electronics II Final Examination Problems Points. 5. 0 3. 5 Total 40 Was the exam fair? yes no The University of Toledo f6fs_elct7.fm - Problem 5 points Given is

More information

Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 -

Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 - Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = $ " % &' ( ) * ),! + = $ + % &' (, *,, -.. = 1.8 -, 345 = 0 - Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

ESE319 Introduction to Microelectronics. Output Stages

ESE319 Introduction to Microelectronics. Output Stages Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class

More information

Electronics II. Final Examination

Electronics II. Final Examination f3fs_elct7.fm - The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

ECE2262 Electric Circuits. Chapter 4: Operational Amplifier (OP-AMP) Circuits

ECE2262 Electric Circuits. Chapter 4: Operational Amplifier (OP-AMP) Circuits ECE2262 Electric Circuits Chapter 4: Operational Amplifier (OP-AMP) Circuits 1 4.1 Operational Amplifiers 2 4. Voltages and currents in electrical circuits may represent signals and circuits can perform

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information