Systematic Design of Operational Amplifiers
|
|
- Irma Higgins
- 5 years ago
- Views:
Transcription
1 Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium Willy Sansen
2 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Ref.: Sansen : Analog design essentials, Springer 2006 Willy Sansen
3 Single-stage CMOS OTA : GBW M7 V DD A v = r o g m1 2 I B v- 2 M1 3 M2 1 v + v OUT C L BW = if r o2 = r o4 = r o 1 r 2π o (C L +C n1 ) 2 M3 M4 V SS GBW = g m1 2π (C L +C n1 ) Willy Sansen
4 CMOS OTA : Maximum GBW GBW = g m1 g m1 = I B 2π C L V GS1 -V T I B v- v C L + C L GBW max = I B V GS1 -V T 1 2π C L v OUT+ v OUT- 0.2 V I B = 10 µa C L = 1 pf GBW max 10 MHz FOM = GBW.C L = 1000 I B [8] [800] MHzpF/mA Willy Sansen
5 Single stage CMOS OTA : f nd M7 V DD GBW = g m1 2π (C L +C n1 ) I B v- M1 3 M2 v + v OUT f nd = g m3 2π C n2 C n2 2C GS3 + C DB3 + C DB1 2 1 C L 4 C GS3 M3 M4 V SS f nd f T3 4 Willy Sansen
6 Simple CMOS OTA : f nd M5 A v 2x - M1 3 M2 + 0 o 2x f f v OUT -90 o C n2 2 1 M3 M4 f = g m3 nd 2π C n2 f nd 2f nd GBW GBW PM = 90 o - arctan + arctan 85 2 f o nd f nd Willy Sansen
7 Single stage CMOS OTA : Design 1 GBW = 100 MHz for C L = 2 pf Techno: L min = 0.35 µm; K n = 60 µa/v 2 & K p = 30 µa/v 2 I DS? W? L? gm = GBW 2π CL = 1.2 ms VGS-VT = 0.2 V IDS = gm V GS-VT 2 = g m 10 = 0.12 ma W L = IDS K'(VGS-VT)2 =100 Lp =Ln =1 µm GAIN! Wp = 100 µm; Wn = 50 µm Willy Sansen
8 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Willy Sansen
9 Miller CMOS OTA 5 M7 1 : B M5 V DD Two nodes 1 4 v C c M1 M2 v 4 v OUT with high Impedance 2 1 M6 R L C L cause two poles M3 M4 C n1 split by C c V SS Willy Sansen
10 Miller CMOS OTA : small-signal v - 2 M3 M1 3 M2 1 M4 v + C c C n1 4 v OUT M6 Z L GBW= 1MHz C L = 10 pf R L = 10 kω g m1 = 7.5 µs g o24 = 0.03 µs 1 C c 4 C n1 = 0.37 pf C c = 1 pf g m6 = 246 µs g Lo6 = 20 µs g m1 g o24 C n1 g m6 g Lo6 C Ln4 = 10.2 pf I DS1 = 1.1 µa I DS6 = 25 µa Willy Sansen
11 Miller CMOS OTA : GBW 5 M7 1 : B M5 g m1 A v1 = go24 A v2 = g m6 glo6 v C c M1 M2 v 4 v OUT BW = g o24 2π A v2 C c R L C L g m1 2 M3 1 M4 C n1 M6 f nd GBW = 2π C c g m6 2π C Ln C n1 C c Willy Sansen
12 Miller CMOS OTA : poles and zero C c 1pF 0.1pF 10fF A v C ct f d f C ct 20 ff 1k 1M Hz A A v2 v0 but is sufficient C c = 0 for C c = 1pF BW C c = 1pF 1k GBW 1M f nd f z f Pole splitting starts at f z = C n1 g m6 2π C c Willy Sansen
13 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Willy Sansen
14 Miller CMOS OTA: Design plan GBW = g m1 2π C c GBW = 100 MHz and C L = 2 pf f nd g m6 1 2π C Ln4 1+ C n1 C c Two equations for Three variables g m1, g m6 and C c?!? Solution : choose g m1 or g m6 or C c!!! Willy Sansen
15 What is wrong with choosing C c = 1 pf? Willy Sansen
16 Miller CMOS OTA: Design vs C c Choose C c 3 C n1 GBW = g m1 2π C c g m6 4 C L g m1 C c 3GBW g m6 2π C Ln GBW = 100 MHz and C L = 2 pf Choose C n1 < C c < C L Choice C c = 1 pf gives g m1 = 0.63 ms and g m6 = 5.0 ms Willy Sansen
17 Miller CMOS OTA: Design vs C c g m g m6 g m6min = 3 GBW (2π C L ) g m1 g m6min C c C copt 4 C L Willy Sansen
18 1 MHz Miller CMOS OTA: Design vs C c ms GBW = 1 MHz C n1 ct g mtot 2g m1 C L = 10 pf C n1 =0.4 pf 1 K = 20 µa/v 2 C n1 ~ g m V GS -V T = 0.2 V L = 10 µm 0.2 g m pf C c C n1 = 0.4 pf Willy Sansen
19 Miller CMOS OTA : Design vs I DS6 Area g m6min = Area C c 3 GBW (2π C L ) Area M6 g m6 g m6min g m6opt 1.3 g m6min + 30 % Willy Sansen
20 Miller CMOS OTA : Design vs I DS1 Area Area M6?!? Area C c C L g m1 Willy Sansen
21 Optimum design for high speed Miller OTA - 1 GBW = g m1 C L = α C c α 2 f nd = 2π C c g m6 2π C L Cn1 /Cc C c = β C n1 = β C GS6 β 3 f nd = γ GBW γ 2 C GS = kw k= F/cm GBW = f nd γ = g m6 2π C L 1 γ (1 + 1/ β) C L = α C c = α β C n1 = α β C GS6 = α β kw 6 W 6 if C L Willy Sansen
22 Optimum design Miller for high speed OTA - 2 Elimination of C L yields GBW = g m6 2π kw 6 1 α β γ (1 + 1/ β) g m = W L L /V GST f T6 W, L in cm GBW = 1 2π L 6 1 α β γ (1 + 1/ β) L 6 / V GST6 L in cm GBW is not determined by C L, only by L (and V GST )!! f T is also determined by L!!! Willy Sansen
23 Optimum design Miller for high speed OTA - 3 Substitution for f T yields f T = g m 2πC GS GBW = f T6 α β γ (1 + 1/ β) GBW is not determined by C L, only by f T f T is determined by L (and V GST )!!! 1.35 f T = 1 L L / V GST L in cm f T in MHz If V GST = 0.2 V, v sat takes over for L < 65 nm (If 0.5 V for L < 0.15 µm) Willy Sansen
24 Maximum GBW versus channel length L GBW GHz 10 1 V GS -V T 0.2 V v sat α 2 β 3 γ 2 or 16 x K nm 100 nm L 1 µm GBW f T6 16 Willy Sansen
25 Design optimization for high speed Miller OTA Choose α β γ Find minimum f T6 for specified GBW Choose maximum channel length L 6 (max. gain) for a chosen V GS6 -V T W 6 is calculated from C L, and determines I DS6 C c is calculated from C L through α g m1 and I DS1 are calculated from C c Noise is determined by g m1 or C c Willy Sansen
26 Design Ex. for GBW = 0.4 GHz & CL = 5 pf Choose α β γ Minimum f T6 for GBW = 0.4 GHz f T6 = 6.4 GHz Maximum channel length L 6 L 6 = 0.5 µm for a chosen V GS6 -V T = 0.2 V L 6 is taken to be the minimum L W 6 is calculated from C L, W 6 = 417 µm and determines I DS6 (K n = 70 µa/v2 ) I DS6 = 2.3 ma and determines C n1 (k = 2 ff/µm) C n1 = 0.83 pf C c is calculated from C L through α C c = 2.5 pf g m1 and I DS1 are calculated from C I c DS1 = 0.63 ma Willy Sansen
27 Optimum design Miller for low speed OTA GBW = f T6 α β γ (1 + 1/ β) f T = f TH i (1 - e - i ) i for small i f TH = 2 µ kt/q 2π L 2 GBW is not determined by C L, only by f T f T is determined by L and i!!! Willy Sansen
28 Design optimization for low speed Miller OTA Choose α β γ Find minimum f T6 for specified GBW Choose channel length L 6 (max. gain), which gives f TH6 Calculate i 6 W 6 is calculated from C L, and determines I DST6 and I DS6 C c is calculated from C L through α g m1 and I DS1 are calculated from C c Noise is determined by g m1 or C c Willy Sansen
29 Design Ex. for GBW = 1 MHz & CL = 5 pf Choose α β γ Minimum f T6 for GBW = 1 MHz f T6 = 16 MHz Maximum channel length L 6 L 6 = 0.5 µm gives f TH6 f TH6 = 2 GHz Inversion coefficient i is i = W 6 is calculated from C L, W 6 = 417 µm and determines I DST6 (K n = 70 µa/v2 ) I DST6 = 0.33 ma and determines I DS6 I DS6 = 2.7 µa and determines C n1 (k = 2 ff/µm) C n1 = 0.83 pf C c is calculated from C L through α C c = 2.5 pf g m1 and I DS1 are calculated from C I c DS1 = 1.6 µa Willy Sansen
30 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other : SR, Output Impedance, Noise,... Willy Sansen
31 Miller CMOS OTA: Specifications 1 1. Introductory analysis 1.1 DC currents and voltages on all nodes 1.2 Small-signal parameters of all transistors 2. DC analysis 2.1 Common-mode input voltage range vs supply Voltage 2.2 Output voltage range vs supply Voltage 2.3 Maximum output current (sink and source) Willy Sansen
32 Miller CMOS OTA: Specifications 2 3. AC and transient analysis 3.1 AC resistance and capacitance on all nodes 3.2 Gain versus frequency : GBW, 3.3 Gainbandwidth versus biasing current 3.4 Slew rate versus load capacitance 3.5 Output voltage range versus frequency 3.6 Settling time 3.7 Input impedance vs frequency (open & closed loop) 3.8 Output impedance vs frequency (open & closed loop) Willy Sansen
33 Miller CMOS OTA: Specifications 3 4. Specifications related to offset and noise 4.1 Offset voltage versus common-mode input Voltage 4.2 CMRR versus frequency 4.3 Input bias current and offset 4.4 Equivalent input noise voltage versus frequency 4.5 Equivalent input noise current versus frequency 4.6 Noise optimization for capacitive/inductive sources 4.7 PSRR versus frequency 4.8 Distortion Willy Sansen
34 Miller CMOS OTA: Specifications 4 5. Other second-order effects 5.1 Stability for inductive loads 5.2 Switching the biasing transistors 5.3 Switching or ramping the supply voltages 5.4 Different supply voltages, temperatures,... Willy Sansen
35 M C O : Other specifications o Common-mode input voltage range o Output voltage range o Slew Rate o Output impedance o Noise Willy Sansen
36 Miller CMOS OTA 5 M7 1 : B M5 V DD GBW = 1 MHz C L = 10 pf R L = 10 kω v C c M1 M2 v 4 v OUT g m1 = 7.5 µs I DS1 = 1 µa R L C L g o24 = 0.03 µs 2 M3 1 M4 M6 V SS g m6 = 246 µs I DS6 = 25 µa C c = 1 pf Willy Sansen
37 Miller CMOS OTA : CM Input Voltage Range 3V V ICM 2V V DD 1V V ICMmax 0V -1V V ICM -2V -3V V SS V ICMmin 0 1V 2V ±2.5V 3V 4V V DD = V SS Willy Sansen
38 Miller CMOS OTA : Output Voltage Range 3V V OUT Rail-to-rail output if no R L V DD 2V V DD V OUTmax M5 1V 0V 4 v OUT -1V V OUT R L C L -2V -3V V SS V OUTmin 0 1V 2V ±2.5V 3V 4V V DD = V SS Willy Sansen
39 Miller CMOS OTA : Slew Rate - 1 v 5 3 M1 M7 1 : B I B1 I B1 - C c M5 4 V DD v OUT Switch input : v + > 1 v - > M6 R L C L SR = V OUT t M3 M4 V SS SR = I B1 C c Willy Sansen
40 Miller CMOS OTA : Slew Rate - 2 v IN v IN t t v OUT v OUT SR SR t SR SR V OUTmax t SR V OUTmax f max 4 V OUTmax SR 4 fmax SR T max 4 Willy Sansen
41 Miller CMOS OTA : Slew Rate - 3 V p 2 V OUT V OUTmax SR 4 fmax SR = 2.2 V/µs M 0.4M 0.6M 0.8M 1MHz f Willy Sansen
42 Design for GBW or SR? SR GBW = 4π I DS1 g m1 I DS1 V = GS1 -V T g m1 2 I DS1 g m1 = nkt q V for MOST (si) x mv for MOST (wi) I CE1 kt g m1 = q 26 mv for Bipolar trans. I CE1 g m1 = (1 + g m1 R E ) kt q V with R E Solomon, JSSC Dec 74, Willy Sansen
43 High SR by g m reduction V DD I B I B SR v- n : 1 M3 M1 M2 1 : n M4 v+ 2π GBW = x (n+1) v OUT C L M5 M6 V SS Ref. Schmoock, JSSC Dec.75, Willy Sansen
44 External vs internal Slew Rate V DD M5 I DS5 SR int = I B C c I B C c 4 v OUT I DS5 SR ext = is larger! C L 1 M6 C L g m6 = 4 CL g m1 C c = I DS5 I DS1 M4 V SS I DS5 C L 2 2I DS1 C c Willy Sansen
45 Slew Rate and settling v IN t t TOT = t Slew + t 0.1 v OUT V OUT 0.1 % t Slew = V OUT SR SR t t 0.1 = 7 2π BW t Slew t 0.1 ln (1000) 7 Willy Sansen
46 Miller CMOS OTA Output Impedance M7 1 : B M5 V DD GBW = 1 MHz C L = 10 pf 5 v C c M1 M2 2 1 M3 M4 v 4 Z OUT M6 V SS g m1 = 7.5 µs R L I DS1 = 1 µa C L Z OUTCL g o24 = 0.03 µs g m6 = 246 µs I DS6 = 25 µa C c = 1 pf Willy Sansen
47 Miller CMOS OTA : Output impedance Z OUT Z OUT 1/g o MΩ A v20 open loop 1/g m6 4 kω f z = g o24 2πC c f z 4.8 khz A v10 A v with C L closed loop f f d f z GBW f nd Willy Sansen
48 Miller CMOS OTA : Noise density 1 dv in1 2 dv in2 2 C c 1 4 v OUT v in v n1 g o24 C n1 g Lo6 C L v neq g m1 v in g m6 v n1 dv 2 4/3 in1 4kT df dv 2 in2 g m1 2/3 4kT g df m6 Willy Sansen
49 Miller CMOS OTA : Noise density 2 dv eq 2 dv in1 2 A v10 2 Dominant on linear frequency scale! 4kT df 2/3 g m6 dv neq2 2 = dv neq2 2 A v10 = go24 dv in2 2 A v1 2 g m1 f z GBW f nd f f z = g o24 2πC c Willy Sansen
50 Miller CMOS OTA : Integrated Noise A 1 GBW f GBW n π = 2 GBW v nieq 2 = 0 dv nieq (f/ GBW) 2 0 v 2 4/3 nieq = 4kT GBW π 2 g m1 dx 1 + x 2 = π 2 C c = 1pF v Rs = 74.5 µv RMS v 2 4 nieq = 3 kt C c Willy Sansen
51 Noise density vs integrated noise A dv ni 2 4/3 = 4kT df g m BW BW n f v ni 2 = dv ni (f/ BW) 2 = 4kT 3C c Noise density (V 2 /Hz) ~ 1/g m (or R S ) Integrated noise (V RMS ) ~ 1/C c Willy Sansen
52 CMOS Miller OTA layout V SS IN+ IN- GBW = 1 MHz C L = 10 pf SR = 2.2 V/µs V DD = 5 V I TOT = 27 µa OUT I B 370 MHzpF/mA V DD Willy Sansen
53 Miller CMOS OTA : Exercise GBW = 50 MHz for C L = 2 pf : use min. I DS6! Techno: L min = 0.5 µm; K n = 50 µa/v 2 & K p = 25 µa/v 2 C GS = kw (= C ox WL) and k = 2 ff/ µm V GS -V T = 0.2 V Find g m6 I DS6 W 6 C n1 = C GS6 C c g m1 I DS1 dv ineq 2 v inrms Willy Sansen
54 Conclusion : Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Willy Sansen
Amplifiers, Source followers & Cascodes
Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror
More informationStability of Operational amplifiers
Stability o Operational ampliiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 05 Table o contents Use o operational ampliiers Stability o 2-stage opamp
More informationFeedback Transimpedance & Current Amplifiers
Feedback Transimpedance & Current Amplifiers Willy Sansen KULeuven, ESATMICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 1005 141 Table of contents Introduction Shuntshunt FB for Transimpedance
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationDesign of crystal oscillators
Design of crystal oscillators Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 22 Table of contents Oscillation principles Crystals Single-transistor oscillator
More informationECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION
ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationLecture 310 Open-Loop Comparators (3/28/10) Page 310-1
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,
More informationLecture 140 Simple Op Amps (2/11/02) Page 140-1
Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and
More informationLECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter
Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationMICROELECTRONIC CIRCUIT DESIGN Second Edition
MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationEE 435. Lecture 16. Compensation Systematic Two-Stage Op Amp Design
EE 435 Lecture 6 Compensation Systematic Two-Stage Op Amp Design Review from last lecture Review of Basic Concepts Pole Locations and Stability Theorem: A system is stable iff all closed-loop poles lie
More informationV in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant
More informationECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution
ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationMicroelectronic Circuit Design 4th Edition Errata - Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationElectronics II. Midterm II
The University of Toledo f4ms_elct7.fm - Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm - Problem 7 points Given in
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationA LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load
A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1 Outline
More informationAdvanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs
Advanced Analog Integrated Circuits Operational Transconductance Amplifier II Multi-Stage Designs Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam
More informationLecture 04: Single Transistor Ampliers
Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor
More informationESE319 Introduction to Microelectronics. Feedback Basics
Feedback Basics Stability Feedback concept Feedback in emitter follower One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability
More informationMaxim Integrated Products 1
19-4187; Rev 4; 7/1 μ μ PART AMPS PER PACKAGE PIN- PACKAGE + * TOP MARK MAX965AZK+ 1 5 SOT3 ADSI MAX965AZK/V+ 1 5 SOT3 ADSK MAX965AUA+ 1 8 μmax-ep* AABI MAX965ATA+ 1 8 TDFN-EP* BKX MAX9651AUA+ 8 μmax-ep*
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationLecture 150 Simple BJT Op Amps (1/28/04) Page 150-1
Lecture 50 Simple BJT Op Amps (/28/04) Page 50 LECTURE 50 SIMPLE BJT OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First
More informationAdvantages of Using CMOS
Advantages of Using CMOS Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized
More informationFrequency Detection of CDRs (1)
Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd =
More informationECE 546 Lecture 11 MOS Amplifiers
ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationStudio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.
Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232-242 Two-stage op-amp Analysis Strategy Recognize
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More information6.2 INTRODUCTION TO OP AMPS
Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OVA & OTA 1 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly
More informationUNIVERSITÀ DEGLI STUDI DI CATANIA. Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo
UNIVERSITÀ DEGLI STUDI DI CATANIA DIPARTIMENTO DI INGEGNERIA ELETTRICA, ELETTRONICA E DEI SISTEMI Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open
More informationLast Name _Di Tredici_ Given Name _Venere_ ID Number
Last Name _Di Tredici_ Given Name _Venere_ ID Number 0180713 Question n. 1 Discuss noise in MEMS accelerometers, indicating the different physical sources and which design parameters you can act on (with
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationECE315 / ECE515 Lecture 11 Date:
ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationCMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators
IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater
More informationECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =
ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More information4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP)
emp. Indep. Biasing (7/14/00) Page 1 4.5 (A4.3) - EMPERAURE INDEPENDEN BIASING (BANDGAP) INRODUCION Objective he objective of this presentation is: 1.) Introduce the concept of a bandgap reference 2.)
More informationECEN 610 Mixed-Signal Interfaces
ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)
More informationESE319 Introduction to Microelectronics. Feedback Basics
Feedback Basics Feedback concept Feedback in emitter follower Stability One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability
More informationPRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION
Practice Problems (5/27/07) Page PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION TECHNOLOGY Problem (044430E3P5) The following questions pertain to a standard npn BJT process. a.) Give the
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the
More informationSample-and-Holds David Johns and Ken Martin University of Toronto
Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters
More informationL4970A 10A SWITCHING REGULATOR
L4970A 10A SWITCHING REGULATOR 10A OUTPUT CURRENT.1 TO 40 OUTPUT OLTAGE RANGE 0 TO 90 DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULA- TION INTERNAL CURRENT LIMITING PRECISE.1 ± 2 ON CHIP REFERENCE
More informationCHAPTER 6 CMOS OPERATIONAL AMPLIFIERS
Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode
More informationAdvanced Analog Integrated Circuits. Operational Transconductance Amplifier I & Step Response
Advanced Analog Integrated Circuits Operational Transconductance Amplifier I & Step Response Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard Boser
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationPreamplifier in 0.5µm CMOS
A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationAnalog Circuit Design Discrete & Integrated
This document contains the Errata for the textbook Analog Circuit Design Discrete & Integrated The Hardcover Edition (shown below at the left and published by McGraw-Hill Education) was preceded by a Spiral-Bound
More informationSHM-14 Ultra-Fast, 14-Bit Linear Monolithic Sample-Hold Amplifiers
INNOVATION and EX C ELL E N C E Ultra-Fast, 1-Bit Linear Monolithic Sample-Hold Amplifiers FEATURES Fast acquisition time: 10ns to ±0.1% 0ns to ±0.0% ns to ±0.01% ±0.001% Nonlinearity 6µV rms output noise
More informationThe transistor is not in the cutoff region. the transistor is in the saturation region. To see this, recognize that in a long-channel transistor ifv
ECE 440 Spring 005 Page 1 Homework Assignment No. Solutions P.4 For each transistor, first determine if the transistor is in cutoff by checking to see if GS is less than or greater than. may have to be
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationMicroelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises
Page Microelectronic Circuit esign Fourth Edition - Part I Solutions to Exercises CHAPTER V LSB 5.V 0 bits 5.V 04bits 5.00 mv V 5.V MSB.560V 000000 9 + 8 + 4 + 0 785 0 V O 785 5.00mV or ) 5.V 3.95 V V
More informationElectronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory
Electronic Circuits Prof. Dr. Qiuting Huang 6. Transimpedance Amplifiers, Voltage Regulators, Logarithmic Amplifiers, Anti-Logarithmic Amplifiers Transimpedance Amplifiers Sensing an input current ii in
More information2N5545/46/47/JANTX/JANTXV
N//7/JANTX/JANTXV Monolithic N-Channel JFET Duals Product Summary Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv) N. to.. N. to.. N7. to.. Features Benefits Applications
More informationEXAMPLE DESIGN PART 2
ECE37 Advanced Analog Circuits Lecture 4 EXAMPLE DESIGN PART 2 Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS analog
More informationPractice 7: CMOS Capacitance
Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More information55:041 Electronic Circuits The University of Iowa Fall Final Exam
Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationMC MC35172 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS.. GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2.1MHz, 2V/µs
MC3372 MC3572 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2MHz, 2/µs SINGLE (OR DUAL) SUPPLY OPERATION FROM +4 TO +44 (±2 TO ±22) WIDE INPUT COMMON MODE
More informationLecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters
Lecture 6, ATIK Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters What did we do last time? Switched capacitor circuits The basics Charge-redistribution analysis Nonidealties
More informationElectronics II. Final Examination
f3fs_elct7.fm - The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
More informationThe current source. The Active Current Source
V ref + - The current source Minimum noise euals: Thevenin Norton = V ref DC current through resistor gives an increase of /f noise (granular structure) Accuracy of source also determined by the accuracy
More informationExact Analysis of a Common-Source MOSFET Amplifier
Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel
More informationSpectral Analysis of Noise in Switching LC-Oscillators
Spectral Analysis of Noise in Switching LC-Oscillators 71 Sub-Outline Duty Cycle of g m -cell Small-Signal Gain Oscillation Condition LC-Tank Noise g m -cell Noise Tail-Current Source Noise (Phase) Noise
More informationID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationElectronics and Communication Exercise 1
Electronics and Communication Exercise 1 1. For matrices of same dimension M, N and scalar c, which one of these properties DOES NOT ALWAYS hold? (A) (M T ) T = M (C) (M + N) T = M T + N T (B) (cm)+ =
More information