Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs

Transcription

1 Advanced Analog Integrated Circuits Operational Transconductance Amplifier II Multi-Stage Designs Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 1

2 Voltage Gain 2

3 Power Dissipation Voltage gain stage Single Multiple 3

4 Frequency Compensation Cascaded amplifiers Each stage contributes a pole Stability: only one dominant pole (f " < f $ of T s ) Ensuring this is called compensation Main compensation techniques Narrowbanding Feedback zero Miller Feedforward 4

5 Narrowbanding T s T - ω "/ ω "0 log ω 5

6 Feedback Zero LHP zero adds lead Closed-loop response modified above zero Compensation only marginally reduces bandwidth H s a s T s log ω Ref: Feedback, Op Amps and Compensation, AN , Intersil, Nov f s

7 Miller Compensation ω "/ ω "0 7

8 Intuitive Appreciation of Pole Splitting H s a s ω "/ ω "0 log ω Capacitive feedback splits the poles 8

9 Compensated a(s) p / 1 R / g 90 R 0 C A Miller gain p 0 g 90 C C / C A + C / g 90 C 0 z = + g 90 C A GBW = ω $ ω "/ T - = β g 9/ C A 9

10 Bandwidth Comparison Single voltage gain stage ω $ β g 9/ C I ω JK ω L 3 Two voltage gain stages ω $ β g 9/ C A O PQ C / ω JK = ω "0 g 90 = g 90 C I NC / CR I S/? 10

11 Advanced Analog Integrated Circuits Miller Zero Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 11

12 Root Locus Ignoring zero With zero 12

13 Bode Plot +180 /T o p / z p 0 13

14 Intuitive Appreciation of Zero 14

15 Mitigating Impact of Zero 15

16 Nulling Resistor T s = T - 1 sc A 1 g 90 R U 1 s p / 1 s p 0 1 s p V R U can be used to tune the zero Poles p / and p 0 unchanged Additional pole p V / X Y Z [ 16

17 Choices for R z 17

18 Ahuja Compensation No zero (ideal cascode) p 2 at higher frequency Translates into smaller C c for given C 2 [ Ahuja, IEEE JSSC, 12/1983 ] p p 1 2» - = ( 1+ g R ) * 2 m2 gm2» - C + C p c C C C2 Cc Cc + C2 C1 $!#!" usually > 1 c 1 R C 1 c gm 1» - a C v0 c Problems: Current I 2 (extra power) Mismatch (in I 2 sources) causes offset I 2 limits slew rate 18

19 Ribner Variant Uses 1 st stage cascode to make feedback unilateral No extra power or slewing limitation 3 rd order response very challenging design problem [ Ribner, IEEE JSSC, 12/1984 ] 19

20 Noise Analysis For full treatment, see A. Dastgheib and B. Murmann, Calculation of total integrated noise in analog circuits, IEEE TCAS I, Nov. 2008, pp

21 Advanced Analog Integrated Circuits Design Example Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 21

22 Design Example 22

23 Specification 23

24 Unknowns Topology Device parameters: M 1 : g 9/, V /, f L/ I a/, L /, W / M 2 : g 90, V 0, f L0 I a0, L 0, W 0 Compensation capacitance, C A Noise excess factors, α /, α 0 Output voltage range 24

25 Structural Parameters Guess (and iterate): Now calculate remaining design parameters 25

26 Gain and Feedback Factor 26

27 Dynamic Range 27

28 Settling 28

29 Power Dissipation Close to weak inversion: increase L 1 (higher gain) reduce r gg1 (lower power?) 29

30 Iteration: r gg1 = 0.1 was 8.8 mw 30

31 Sanity Check: Single Gain Stage About half the power of 2-stage Provided gain & dynamic range can be met Practical lower bound 31

32 Finalize Design Iterate over all parameters (use Matlab lookup ) Estimate and add extrinsic capacitances Other design elements Static settling error Slewing Biasing Device geometry Corners Layout 32

33 Advanced Analog Integrated Circuits Special OTA Topologies Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 33

34 Nested Miller Compensation Ref: R. Eschauzier et al, A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure, IEEE JSSC, Dec. 1992, pp

35 Settling Behavior Very challenging design problem Accurate and fast settling (nearly?) impossible Good choice for broad-band, high gain & other situations that do not require fast settling PM = 85 o Ref: Nguyen & Murmann, The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter, IEEE TCAS I, June 2010, pp

36 Feedforward OTA Ref: Shibata et al, A DC-to-1 GHz Tunable RF DS ADC Achieving DR=74dB and BW=150MHz at f o =450MHz Using 550 mw, JSSC 12/2012, pp