Amplifiers, Source followers & Cascodes

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Amplifiers, Source followers & Cascodes"

Transcription

1 Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium Willy Sansen

2 Operational amplifier Differential pair v- : B v + Current mirror v OUT Current mirror Singletransistor amplifier Willy Sansen

3 Table of contents Single-transistor amplifiers Source followers Cascodes Willy Sansen

4 Single-transistor amplifier - I L v GS - gm v GS r DS - A v = g m r DS = 2 I DS V E L = 2 V E L V GS -V T I DS V GS -V T A v 00 if V E L 0 V and V GS -V T 0.2 V Willy Sansen

5 Single-transistor amplifier - 2 High gain? Low V GS -V T and large L!!! Willy Sansen

6 MOST or bipolar amplifier? MOST A v = V E L (V GS -V T )/2 A v 00 if V E L 0 V and V GS -V T 0.2 V Bipolar A v = V E kt/q 3 vs 2 stages for 0 6 A v 000 if V E 26 V since kt/q = 26 mv Willy Sansen

7 Gain, Bandwidth and Gain-bandwidth I L + - C L A v0 = g m r DS BW = 2π r DS C L For all single-stage Operational amplifiers g m GBW = 2π CL Willy Sansen

8 Gain A v, BW and GBW A v A v0 BW -20 db/decade A v0 = g m r DS GBW g m GBW = 2π CL A v0 φ (A v ) 0 o f φ (A v ) = - 45 o -90 o at BW Willy Sansen

9 Single-transistor amplifier : Exercise GBW = 00 MHz for C L = 3 pf Techno.: K n 50 µa/v 2 L min = 0.5 µm I DS? L? W? GBW.C L? I DS Willy Sansen

10 Gain, Bandwidth and Gain-bandwidth I L A v0 = g m r DS R S + - BW = 2π R S C GS C GS g m GBW = 2π CGS r DS R S = f T r DS RS ~ WC ox V GS -V T W? L? V GS -V T? Willy Sansen

11 Gain, Bandwidth and Gain-bandwidth R S C F I L + A v0 = g m r DS - BW = 2π RS A v0 C F GBW = 2π RS C F Willy Sansen

12 Miller effect I L C F R + S R S C FM I L A v0 = g m r DS C FM =(+A v0 ) C F Miller, Dependence of the input impedance of a three-electrode vacuum tube upon the load in the plate circuit, Scient. Papers Bur. Standards, 920, Willy Sansen

13 Miller capacitance feedback effects R S C F I L + A v A v0 BW - j f/f A z v = A v0 + j f/f p + g m R S g m f z = 2π CF - φ (A v ) 0 o f p GBW f z f For phase, a positive zero is like a negative pole!!! -90 o - 80 o Willy Sansen

14 Amplifier with local R- (series) feedback g mr = g m C inr i out ~ RS R outr + g m R S RS R outr = r DS (+ g m R S ) (g m r DS ) R S C GS C inr = + gm R S But R S gives extra noise! Willy Sansen

15 Amplifier with local L- feedback Z inl i out R outl g ml = g m + g m L S s R outl = r DS (+ g m L S s) L S L S Z inl = g m CGS + + L S C GS s 2 s C GS No extra noise! Z inl = L S ω T + L S s+ s CGS Willy Sansen

16 Amplifier with local MOST-R- Feedback M M2 i out V DS2 = V GS2 -V GS 0.2 V r DS2 = KP W 2 /L 2 (V GS2 -V T ) R outr = r DS (+ g m r DS2 ) C inr = C GS +C GS2 + gm r DS2 Willy Sansen

17 Diode-connected MOST : parallel Feedback I DS I DS V DS = V GS -V T V DS = V GS G = D + V DS = V GS - saturation V GS I DS = K W n (V DS -V T ) L 2 0 V T V DS Willy Sansen

18 Diode-connected MOST: small-signal I DS i DS G = D V DS = V GS - v GS g m v GS r DS r ds = /g m // r DS /g m Willy Sansen

19 Diode-connected MOST at high frequencies I DS i DS + v GS + G = D DS = V GS -V C GS - g m v GS r DS BW = g m C DS 2π (C GS +C DS ) f T 2 Willy Sansen

20 Wideband amplifier M2 V DD V OUT = V DD -V GS2 (V OUT ) M A v0 = g m (W/L) g m2 = (W/L) 2 V GS2 -V T = VGS -V T R OUT = /g m2 Willy Sansen

21 Linear wideband amplifier 2I B V DD V OUT = V GS2 M M2 A v0 = g m (W/L) g m2 = (W/L) 2 V GS2 -V T = VGS -V T R OUT = /g m2 Current mirror with only nmosts Same V OUTDC as V INDC No body bias effect Good PSRR Double power consumption Willy Sansen

22 Wideband amplifiers 2I B 2I B M M2 M M2 A v0 = g m (W/L) g m2 = (W/L) 2 V GS2 -V T = VGS -V T A v0 = g m R out R out = /g m2 R out = r DS //r DS2 Willy Sansen

23 Class A versus class AB amplifier + i out M2 i out M2 M C L M C L = A v = A v Class A stage Class AB stage Willy Sansen

24 CMOS inverter-amplifier V DD V DD 0 M2 0 M2 M M C L C L Digital invertor Analog amplifier Willy Sansen

25 Operating points nmost & pmost V DD I DS M2 I DS nmost M 4 M2 pmost M C L V DD = V DSn + V DSp V DSn = V OUT V DSp = V DD -V OUT = V GSn + V GSp V GSn = V IN V GSp = V DD -V IN V OUT Willy Sansen

26 Transfer characteristic V DD i DS M2 M C L V DD V DD 2 0 i DS I DSA = 0 = 5 V DD 2 Analog amplifier = = V DD 0 Willy Sansen

27 Analog amplifier : DC V DD i DSA V in = V DD V out = 2 V DD 2 M2 I DSn = K n (V in -V T ) 2 v L in n C L M W n W p I DSp = K p (V DD -V in -V T ) 2 L p W n W n K I DS = K n ( -V T ) 2 n = K p 2 L n W p L p L n V DD Willy Sansen

28 Analog amplifier : AC model V DD i DSA M2 M + C L - r DSn r DSp C L g mn v iv g mp v iv For the same I DS en V GS -V T : g mn = g mp = g m Willy Sansen

29 Analog amplifier: AC gain Av V DD i DSA If V En L n =V Ep L p = V E M2 M C L g DSn = g DSp = g DS (g DS = /r DS ) 2g A v0 = - m = - 2g DS V DD 2 2V E -V T Willy Sansen

30 Analog amplifier : BW & GBW V DD i DSA M2 M C L A v0 = 2g m R out R out = r DS 2 BW = 2π Rout C L 2g m GBW = 2π CL Willy Sansen

31 Analog amplifier: poles due to CGS V DD A v0 = 2g m R out R S M2 2g m C GS M C L GBW = 2π CL C GSt = C GS + C GS2 But if R S C GSt > r DS C L : GBW = f T r DS R S Willy Sansen

32 Analog amplifier: poles due to CDG V DD C DG f d f nd R S C DG M2 C L g m R S f z M CL 2π R out C L A v0 ( - sc DGt /g m ) = + s (R out C L + A v0 R S C DGt ) + s 2 R S R out C DGt C L f Willy Sansen

33 Analog amplifier: other poles V DD A v0 = 2g m R out C DG R S M2 GBW = M C L 2g m 2π C L C DGt = C DG + C DG2 But if R S C DGt > 2π GBW : GBW = 2π RS C DGt Willy Sansen

34 Class AB operation V DD i C M2 i C2 I C2 I C i L i C C L I DSA i L M 0 i L = i C2 -i C V DD 2 VDD Willy Sansen

35 Table of contents Single-transistor amplifiers Source followers Cascodes Willy Sansen

36 Single-transistor stages Common source Common drain Common gate i out v vin out v Rout in V B I V B B + i out R in i in I B i out = g m = i out = i in R out /g m R in /g m Amplifier Source follower Cascode Voltage buffer Current buffer Willy Sansen

37 Source follower with V BS = 0 (p-well) R S Z OUT = gm V GS = V T0 + I B K W/L V GS = ct if I B = ct V B I B R B C L V OUT = V IN -V GS V OUT = V IN A v = Willy Sansen

38 Source follower with V BS 0 (n-well) R S Z OUT < gm V GS = V T + V GS ct I B K W/L VB I B R B C L V OUT = V IN -V GS A v = V T = V T0 + γ [ 2Φ F +V OUT - 2Φ F ] n Willy Sansen

39 Source follower non-linearity R S V OUT γ = 0 slope VB I B C L γ = 0.8 V /2 slope /n 0 V T V IN Willy Sansen

40 Emitter follower R S R OUT R S R IN VB I B C L V B R E R S +r B A v = R OUT = + g m β+ Limited isolation! R IN = r π +r B + (β+)r E Willy Sansen

41 Source follower with C L load g m 0mS g mr f d f nd f z A v = ( + s C GS /g m ) + s B + s 2 C 2 R S /g m ms 0.mS A v 0. f d M G Hz g mr f B = R S C DG + C DS g m C GS g m R S + (+ ) r DS 0.0 C 2 = C DS C DG f C DS C GS + C DG C GS C DS = C L + C DS M G Hz Willy Sansen

42 Source follower with C L load g m 0mS ms 0.mS A v f d f g nd mr f g z mr g mr = R S g mu f d M G Hz g mr f g mr = C DGt C DG C DGt = C L + C DS + C GS C DG C DS C GS C DS + C GS 0.00 M G Hz f g mu = R S Willy Sansen

43 Source follower : Output impedance g m 0mS g mr f z f d f nd g mr = C GS + C DS R S C DG ms g mu 0.mS Z out 0kΩ k g mu f d f nd M G Hz f g mu f z = C GS + C DS R S C GS + C DG 00 0 g mr M Inductive G Hz f 2π R S C GS f d,higm = 2π R S C DG Willy Sansen

44 Emitter follower : Output impedance g m 0mS ms 0.mS Z out 0kΩ k 00 0 f d f nd C π + C CE g f mr z g mr = R S C π + C µ g mu g mu g mr f d M G Hz M f nd Inductive G L = R S ω T Hz f f g mu f z = C je + C CE R S C je + C µ 2π R S //r π (C π +C µ ) Willy Sansen

45 Source follower as active L V B R S C GS I B Z OUT C L g m g m Z OUT L R S f Z OUT ( + R g S C GS s) m L R S 2π f T f T g m R S f T g m up to f T = 2π CGS Willy Sansen

46 Source follower as active L R S L L L I B I B I B2 I B I B2 L R S 2π f T L /g mp 2π f Tn L /g mp 2π f Tn V DSn = V GSn V DSn = V GSn + V GSp V DSn = V GSp Willy Sansen

47 Floating inductor with parallel C R tune R tune L = R tune ω T2 T 2 V out+ V out- V out+ V out- V in- T C V in+ C I B A v = g m g m2 with HF peaking! Willy Sansen

48 Table of contents Single-transistor amplifiers Source followers Cascodes Willy Sansen

49 Single-transistor stages Common source Common drain Common gate i out v vin out v Rout in V B I V B B + i out R in i in I B i out = g m = i out = i in R out /g m R in /g m Amplifier Source follower Cascode Voltage buffer Current buffer Willy Sansen

50 Cascode with resistive load A R? R L A R = R L + i DS R in? i in I B g m r DS R Lc R L A R = R i in = in iin Willy Sansen

51 Cascode with resistive load R L i L g m R B i ds i in + i ds r DS i L i in I B R B i in R Lc = g m r DS R B R Lc R L Willy Sansen

52 Cascode with active load A R i B R Lc + i DS r DS A R R in R B i in I B R B g m r DS R Lc R L A R = R in = iin iin R Lc = g m r DS R B 00 R B Willy Sansen

53 Cascode versus single-transistor I B I B + M2 M M A v = (g m r DS ) R out = r DS A v = (g m r DS ) (g m r DS ) 2 R out = r DS (g mr DS ) 2 Willy Sansen

54 Cascode versus single-transistor I B I B + M2 M C L M C L BW = 2π R out C L g m GBW = for both! 2π C L Willy Sansen

55 Cascode versus single-transistor I B A v + M I B M2 C L A v2 = g m2 r DS2 A v = g m r DS Single transistor GBW M C L Cascode : High gain At low freq. f g m GBW = 2π CL Willy Sansen

56 Miller effect in cascode? A v2 = g m2 r o2 A v = g m r o I B R S A v R S C M f nd r o2 C L R S C M + M2 v m C L R St f d R S C M M A v2 r o C L f g m GBW = 2π CL C L No Miller if R S < R St = r o2 CM g m2 g m Willy Sansen

57 Cascode with capacitance Cm at middle point A v2 = g m2 r o2 A v = g m r o2 I B C m r o C m f nd r o2 C L R S + M2 v m C L C mt f d C m /g m2 M C m A v2 r o C L g m GBW = 2π CL C mt = g m2 r o2 C L = A v2 C L f Willy Sansen

58 Telescopic Cascode +3 M4 A v = g m R out +2 + M3 M2 I B R out R out = r DS g m2 r DS2 2 M C L BW = 2π Rout C L g m GBW = 2π CL Willy Sansen

59 Folded Cascode I B A v = g m R out M2 + R out = r DS g m2 r DS2 M i ds BW = 2π Rout C L I B2 C L g m GBW = 2π CL I DS = I B -I B2 I B / 2 Willy Sansen

60 Cascode versus cascade I B I B I B2 + M2 M M M2 A v = (g m r DS ) (g m r DS ) 2 A v = (g m r DS ) (g m r DS ) 2 Willy Sansen

61 Cascode versus cascade I B Two-stage Miller amplifier + M2 I B C c I B2 C L M M M2 CL g m GBW = 2π CL g m GBW = 2π Cc Willy Sansen

62 Regulated cascode or gain boosting I B I B I B2 M2 + M2 M M M3 A v = (g m r DS ) (g m r DS ) 2 A v = (g m r DS ) (g m r DS ) 2 (g m r DS ) 3 Hosticka, JSSC Dec.79, pp. -4; Sackinger, JSSC Febr.90, pp ; Bult JSSC Dec.90, pp Willy Sansen

63 Regulated cascode, Cascode & single-transistor A v Reg.cascode A v = g m r DS I B I B2 A v3 A v2 = g m2 r DS2 A v3 = g m3 r DS3 C L M2 A v2 Cascode M M3 A v Single trans. GBW GBW = g m 2π CL f Willy Sansen

64 Gain boosting +V B A gb I B A A gb BW gb M2 C L M A casc A v = A gb (g m r DS ) (g m r DS ) 2 GBW gb f z = GBW g m 2π C L Willy Sansen f

65 Pole-zero doublet and settling time A v V OUT A v0 V IN τ GBW τ pz f pz BW f pz GBW f t t V OUT = V IN [ - exp (- ) - exp (- )] 0 τ GBW Kamath, etal, JSSC Dec.74, pp f pz GBW τ pz f pz = GBW = t 2π τ pz 2π τ GBW Willy Sansen

66 Single-transistor stages i out vin + i out i in V B V B I B I B i out = g m = i out = i in Z out /g Z m in /g m Amplifier Source follower Cascode Willy Sansen

67 MOST amplifier & follower i out i out R S R out R out R B R S R out I B + - R out R B R B > /g m R B > /g m A G A V g m /R B R in R out r o g m R B r o /g m /g m Willy Sansen

68 Bipolar transistor (β >> ) R in R in i out i out R S R out R out R B R S R out I B + - R out R B R B > /g m R B > /g m A G A V g m /R B R in r B +r π r B +r π +βr B r B +r π +βr o r B +r π +βr B R out r o g m R B r o /g m + R S /β /g m + R S /β Willy Sansen

69 In- & output resistances MOST cascode R L R out R L R out R out R out R in R in R in R in R B i in I B i in R B i in I B i in R B > /g m R B > /g m A R R in R L R L g m r o R B - /g m /g m R B R out g m r o R B g m r o R B Willy Sansen

70 In- & output resistances Bipolar trans. cascode R L R L R out R out R out R out R in R in R in R in R B i in I B i in R B i in I B i in R B > /g m R B > /g m A R R L R L g m r o R B - R in /g m /g m R B //(r B +r π ) r B +r π R out g m r o R B g m r o (R B //(r B +r π )) βr o βr o Willy Sansen

71 Calculation of AR for a MOST cascode R out R in + v - g m v r o g m v + R B i in R B i in i in - R B > /g m v = - A R = g m r o R B = -g m vr o = - R B yields = - R B i in ( + g m r o ) and g m r o >> Willy Sansen

72 Table of contents Single-transistor amplifiers Source followers Cascodes Willy Sansen

Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

More information

Feedback Transimpedance & Current Amplifiers

Feedback Transimpedance & Current Amplifiers Feedback Transimpedance & Current Amplifiers Willy Sansen KULeuven, ESATMICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 1005 141 Table of contents Introduction Shuntshunt FB for Transimpedance

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

Stability of Operational amplifiers

Stability of Operational amplifiers Stability o Operational ampliiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 05 Table o contents Use o operational ampliiers Stability o 2-stage opamp

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 140 Simple Op Amps (2/11/02) Page 140-1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

More information

Design of crystal oscillators

Design of crystal oscillators Design of crystal oscillators Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 22 Table of contents Oscillation principles Crystals Single-transistor oscillator

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Lecture 37: Frequency response. Context

Lecture 37: Frequency response. Context EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

ECEN 326 Electronic Circuits

ECEN 326 Electronic Circuits ECEN 326 Electronic Circuits Frequency Response Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering High-Frequency Model BJT & MOS B or G r x C f C or D r

More information

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier I & Step Response

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier I & Step Response Advanced Analog Integrated Circuits Operational Transconductance Amplifier I & Step Response Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard Boser

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OVA & OTA 1 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers 6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

More information

Practice 7: CMOS Capacitance

Practice 7: CMOS Capacitance Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

Exact Analysis of a Common-Source MOSFET Amplifier

Exact Analysis of a Common-Source MOSFET Amplifier Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

At point G V = = = = = = RB B B. IN RB f

At point G V = = = = = = RB B B. IN RB f Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

More information

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

Circuit Topologies & Analysis Techniques in HF ICs

Circuit Topologies & Analysis Techniques in HF ICs Circuit Topologies & Analysis Techniques in HF ICs 1 Outline Analog vs. Microwave Circuit Design Impedance matching Tuned circuit topologies Techniques to maximize bandwidth Challenges in differential

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

6.2 INTRODUCTION TO OP AMPS

6.2 INTRODUCTION TO OP AMPS Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3 ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Last Name _Di Tredici_ Given Name _Venere_ ID Number

Last Name _Di Tredici_ Given Name _Venere_ ID Number Last Name _Di Tredici_ Given Name _Venere_ ID Number 0180713 Question n. 1 Discuss noise in MEMS accelerometers, indicating the different physical sources and which design parameters you can act on (with

More information

Electronics II. Midterm II

Electronics II. Midterm II The University of Toledo f4ms_elct7.fm - Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm - Problem 7 points Given in

More information

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web:     Ph: Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 0-4546 CLASS TEST 08-9 ELECTCAL ENGNEENG Subject

More information

Stability and Frequency Compensation

Stability and Frequency Compensation 類比電路設計 (3349) - 2004 Stability and Frequency ompensation hing-yuan Yang National hung-hsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

CMOS Analog Circuits

CMOS Analog Circuits CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

Preamplifier in 0.5µm CMOS

Preamplifier in 0.5µm CMOS A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

Bipolar junction transistors

Bipolar junction transistors Bipolar junction transistors Find parameters of te BJT in CE configuration at BQ 40 µa and CBQ V. nput caracteristic B / µa 40 0 00 80 60 40 0 0 0, 0,5 0,3 0,35 0,4 BE / V Output caracteristics C / ma

More information

EEE 421 VLSI Circuits

EEE 421 VLSI Circuits EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

More information

ESE319 Introduction to Microelectronics. Feedback Basics

ESE319 Introduction to Microelectronics. Feedback Basics Feedback Basics Stability Feedback concept Feedback in emitter follower One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability

More information

Digital Integrated Circuits

Digital Integrated Circuits Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1 Lecture 50 Simple BJT Op Amps (/28/04) Page 50 LECTURE 50 SIMPLE BJT OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

Microelectronics Main CMOS design rules & basic circuits

Microelectronics Main CMOS design rules & basic circuits GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

More information

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14 Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Advantages of Using CMOS

Advantages of Using CMOS Advantages of Using CMOS Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

ECEN 610 Mixed-Signal Interfaces

ECEN 610 Mixed-Signal Interfaces ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

6.301 Solid-State Circuits Recitation 14: Op-Amps and Assorted Other Topics Prof. Joel L. Dawson

6.301 Solid-State Circuits Recitation 14: Op-Amps and Assorted Other Topics Prof. Joel L. Dawson First, let s take a moment to further explore device matching for current mirrors: I R I 0 Q 1 Q 2 and ask what happens when Q 1 and Q 2 operate at different temperatures. It turns out that grinding through

More information

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs Advanced Analog Integrated Circuits Operational Transconductance Amplifier II Multi-Stage Designs Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard

More information

ECE 6412, Spring Final Exam Page 1

ECE 6412, Spring Final Exam Page 1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

More information

Lecture 28 Field-Effect Transistors

Lecture 28 Field-Effect Transistors Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

More information

Frequency Detection of CDRs (1)

Frequency Detection of CDRs (1) Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd =

More information

ECE315 / ECE515 Lecture 11 Date:

ECE315 / ECE515 Lecture 11 Date: ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

More information

Electronics II. Final Examination

Electronics II. Final Examination The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 2

55:041 Electronic Circuits The University of Iowa Fall Exam 2 Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

More information

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law

More information

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE

CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE To understand Decibels, log scale, general frequency considerations of an amplifier. low frequency analysis - Bode plot low frequency response BJT amplifier Miller

More information

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012 1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal

More information

ECE 255, Frequency Response

ECE 255, Frequency Response ECE 255, Frequency Response 19 April 2018 1 Introduction In this lecture, we address the frequency response of amplifiers. This was touched upon briefly in our previous lecture in Section 7.5 of the textbook.

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

Chapter 10 Feedback. PART C: Stability and Compensation

Chapter 10 Feedback. PART C: Stability and Compensation 1 Chapter 10 Feedback PART C: Stability and Compensation Example: Non-inverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits

More information

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH ) Lecture 30 Compensation of Op AmpsII (/26/04) Page 30 LECTURE 30 COMPENSATION OF OP AMPSII (READING: GHLM 638652, AH 260269) INTRODUCTION The objective of this presentation is to continue the ideas of

More information

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16] Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an n-channel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

More information

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

More information