Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Transcription

1 OVA & OTA 1

2 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly used for board-level circuitry OTA-Operational Transconductance Amplifier Ideally a voltage controlled current source Typically restricted to capacitive (or moderate resistive) loads Primarily used in integrated circuits The op-amp (OVA and OTA) is a fundamental building block in Mixed Signal design. Employed profusely in data converters, filters, sensors, drivers etc. Continued scaling in CMOS technology has been challenging the established paradigms for op-amp design. 2

3 With downscaling in channel length (L) Transition frequency increases (more speed) Open-loop gain reduces (lower intrinsic gain) Supply voltage is scaled down (lower headroom) VDD is scaling down but V TH is almost constant (Design headroom is shrinking faster) Random offsets due to device mismatches 1 V TH WL Integration of Analog into Nano-CMOS? Design low-vdd op-amps. Replace vertical stacking (cascoding) by horizontal cascading of gain stages Explore more effective op-amp compensation techniques. Offset tolerant designs. Also minimize i i power and layout area to keep up with the digitalit trend. Better power supply noise rejection (PSRR) Even if we employ wide-swing biasing for low-voltage designs, three- or higher stage opamps will be indispensable in realizing large open-loop DC gain. 3

4 The op amp (operational amplifier) is a high gain, dc coupled amplifier designed tobe used with negative feedback to precisely define a closed loop transfer function. The basic requirements for an op amp: Sufficiently large gain (the accuracy of the signal processing determines this) Differential inputs Frequency characteristics that permit stable operation when negative feedback is applied Other requirements: High input impedance Low output impedance High speed/frequency OP AMP CHARACTERIZATION Linear and Static Characterization of the CMOS Op Amp A model for a nonideal op amp that includes some of the linear, static nonidealities: 4

5 where Rid = differential input resistance Cid = differential input capacitance Ricm = common mode input resistance Ricm = common mode input capacitance VOS = input-offset voltage CMRR = common-mode mode rejection ratio (when v1=v2v2 an output results) 2 = voltage-noise spectral density (mean-square volts/hertz) e n Linear and Dynamic Characteristics of the Op Amp Differential and common-mode frequency response: Differential-frequency response: Vout s Av s V1 s V2 s Ac s V1 s V2 s 2 A v A v0 s s s s p p p p i i 5

6 Other Characteristics of the Op Amp Power supply rejection ratio (PSRR): Input common mode range (ICMR): ICMR = the voltage range over which the input common-mode signal can vary without influence the differential performance Slew rate (SR): maximum current available to charge and discharge a capacitance SR = output voltage rate limit of the op amp Settling time (Ts): the time needed for the output of the output of the op amp to reach a final value value when excited by a small signal (SR is a large-signal phenomenon). Small-signal settling time can be completely determined from the location of the poles and zeros in the small-signal equivalent circuit. 6

7 OP AMP CATEGORIZATION Amplifiers generaly consist of a cascade of V-I (transconductance stage) or I-V (load stage) Classification of CMOS Op Amps 7

8 Output configuration Single ended Differential Predominantly used for integrated high-performance or high precision amplifiers Requires common mode feedback circuit Class-A Output cannot source/sink currents larger than quiescent point bias current Class-AB Output can provide large drive currents on demand Dynamic, comparator-based Still a research topic Two-stage single ended Miller CMOS OTA 8

9 Classical two-stage CMOS op amp broken into voltage-to-current and current-to-voltage stages: Folded cascode CMOS op amp broken into stages: 9

10 Two-stage Single ended Folded-Cascode CMOS OTA 10

11 COMPENSATION OF OP AMPS Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp. L s A s F s CLG s As 1 A s F s A j F j L j 1 0dB 0dB 0dB arg A j F j M db db 2 argl j0db 11

12 Why Do We Want Good Stability? Consider the step response of second-order system which closely models the closed-loop gain of the op amp connected in unity gain. A good step response is one that quickly reaches its final value. Therefore, we see that phase margin should be at least 45 and preferably 60 or larger. (A rule of thumb for satisfactory stability is that there should be less than three rings.) Note that good stability is not necessarily the quickest rise time. 12

13 Root Locus 1st order feedback system A so-called root locus plot shows the movement of the poles in the s plane as we vary the low-frequency loop gain T0 2nd order feedback system 13

14 3rd order feedback system Consider a feedback network consisting of a forward amplifier with three identical poles, and a feedback network with a constant transfer function f The poles of A(s) are therefore the solution to 14

15 MATLAB: The transfer function with three poles s = tf('s'); p1=-1; p2=-2; p3=-4; T = 1 / [(1-s/p1)*(1-s/p2)*(1-s/p3)]; rlocus(t) 15

16 Adding a Zero: s = tf('s'); z=-5; p1=-1; 1; p2=-2; 2; p3=-4; T = (1-s/z) / [(1-s/p1)*(1-s/p2)*(1-s/p3)]; rlocus(t) 16

17 Benchmarking In order to compare the merit of various compensation techniques, it makes sense to inspect the loop s unity gain frequency before and after the compensation is applied Rationale: The maximum bandwidth we can possibly expect from a feedback amplifier is the unity gain frequency of the loop Regardless of the order of the feedback system, the closed-loop response departs from 1/f as T(s) crosses unity Consider a loop transfer function with n dominant poles that occur before the unity crossover The product of the low frequency loop gain and all dominant poles is called the loop gain pole product (LP product) Note that in a first-order system, the LP product is simply the gainbandwidth product 17

18 Feedback Zero Compensation Leave amplifier poles unchanged and introduce a zero in the feedback network Efficiency of Feedback Zero Compensation 18

19 To first order, since we do not change the poles, the LP product and ω u are (approximately) unchanged. Feedback zero compensation is therefore bandwidth efficient, since we do not need to sacrifice bandwidth to stabilize the circuit. To second order, the LP product will change slightly due to loading from the capacitance added in the feedback network Narrowbanding Compensation Idea: Make one of the loop poles dominant, leave other poles unchanged Efficiency of Narrowbanding ω p1 that gives a maximally flat magnitude response for the closed-loop amplifier? 19

20 The crossover and bandwidth is limited to some fraction of ω p2 At first glance, this makes narrowbanding appear to be inefficient However,, provided that ω p2 is close to the transit frequency of the process technology, this compensation approach is acceptable and hard to surpass in terms of absolute achievable closed-loop speed Example: p Single Gain Stage with Current Buffer Example Realizations Cgs introduces a non-dominant pole at high frequencies ω p2 =ω T CL is adjusted until the circuit achieves the desired phase margin This type of narrowbanding is called load compensation, since stability is ensured by properly sizing the load capacitance CL 20

21 Two-Stage OTA The two-stage amplifier shown below has two comparable poles, assuming thatthereisno additional significant pole from the feedback network If the feedback network is resistive, we may be able to compensate the amplifier by introducing a feedback zero What can we do if the feedback is capacitive? Narrowbanding is not a good idea, since both poles are at low frequencies Miller Compensation Purposely p y connect a capacitor across the second transconductor! Two interesting things happen Low frequency input capacitance of second stage becomes large moves the first pole to a lower frequency Qualitatively speaking, at high frequencies, Cc turns the second stage into a diode connected device low impedance, i.e. large ω p2 21

22 Using the dominant pole approximation: RHP zero: We can approximate further as shown below GBW set by gm1 and Cc Pole Splitting : Increasing Cc reduces ω p1, and increases ω p2 22

23 A very nice knob for adjusting the phase margin of the circuit! Graphical View of Pole Splitting Miller Compensation of the Two-Stage Op Amp The various capacitors are: Cc = accomplishes the Miller compensation CM = capacitance associated with the first-stage mirror (mirror pole) CI = output capacitance to ground of the first-stage CII = output capacitance to ground of the secondstage 23

24 Compensated Two-Stage, Small-Signal Frequency Response Model Simplified Use the CMOS op amp to illustrate: Assume that: gm3 CC Cgd 6, gm3 gds3 gds1, u GB C M g g, g g m1 mi m6 mii 1 1 RI, g g g g ds2 ds4 ds6 ds7 R II C C C C, C C C C C I db2 db4 gs6 II L db6 db7 gd 7 24

25 Nodal Equations: 2 G s C C V sc V g V I I c c out mi in g sc V G s C C V mii c 2 II II c out 0 2 Vout s gmi gmii scc V s GG sg C C G C C g C s CC CC CC in I II II I II I II c mii c I II c I c II 1 s A 0 out gmii / C V s c 2 V s 1 s R C C R C C g R R C s R R C C C C C C in I I II II II c mii I II c I I I II c I c II A 0 gg I II gm1 gm6 GG g g g g I II ds2 ds4 ds6 ds7 D s s s 1 1 s 1 1 1s p p p p p p s s p 2 p 1 D s 1 1 as bs p p p p 1 a, 1 p2 a b

26 p gds gds gds gds R C C R C C g R R C g R R C g C I I II II II c mii I II c mii I II c m6 c p 2 C C C I c II 6 a R C C R C C g R R C g g b R R C C C C C C C C gmii gm6 Right-half plane zero: z1 C C The unity gain bandwidth: I I II II II c mii I II c mii m I I I II c I c II II L c c gg I II g g GB A0 p1 GG g RR C C C 1 mi m1 I II mii I II c c c ω p2 must be greater than unity-gainbandwidth or satisfactory phase margin will not be achieved. Influence of the Mirror Pole C C C C C C M 3 db1 db3 gs3 gs4 The transfer function from the input to the output t voltage of the first stage s 1 V s g /2 g g g g 2 g / C 1 V in s gds2 gds4 gm3 gds1 gds3 sc3 g ds2 g s ds 4 1 g / C 01 m1 m3 ds1 ds3 m1 m3 3 m3 3 26

27 z 2 g / C 3 m3 3 p g / C 3 m3 3 The requirement for 45 phase margin is: M 180 arg A jf j 180 arctg arctg arctg 45 p1 p2 z1 p, i 1,2, z pi i z1 1 Let ω = GB and assume that ω z1 >=10GB, GB GB arctg arctg arctg 0.1 p1 p2 27

28 GB 135 arctg A0arctg arctg 0.1, A0 1 p2 GB GB arctg arctg 5.7 p2 p2 GB GB arctg p GB p2 p2 If 60 phase margin is required, then the following relationships apply: g C 10GB 2.2GB z1 p2 10g g 10 g C m6 m1 g C c c m6 m1 c m 6 m 1 2.2g Cc 0.22C C c 2 CMOS op amp Slew Rate (SR) Slew rate occurs when currents flowing in a capacitor become limited it and is given as I lim dv C C dt 28

29 I5 I6 I5 I7 I5 SR min,, I I Cc C L Cc 6 5 I5 I7 I5 I5 SR min,, if I I Cc C L Cc 7 5 Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate of the two-stage op amp should be, I5/Cc. RIGHT-HALF PLANE ZERO Controlling the Right-Half Plane Zero Why is the RHP zero a problem? Because it boosts the magnitude but lags the phase - the worst possible combination for stability. Solution of the problem: The compensation comes from the feedback path through Cc, but the RHP zero comes from the feedforward path through Cc so eliminate the feedforward path! 29

30 Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor Vout s A V s s R C C R C g R R C s R R C C C in I I II II II mii I II c I II II I c p gds gds gds gds R C C R C g RR C g RR C g C g g g I I II II II mii I II c mii I II c m c p 2 C C C I c II a R I C I C II R IIC II g mii RR I II g mii C c b R R C C C C C C I II II I c II I c Poles are approximately what they were before with the zero removed For 45 phase margin, ω p2 must be greater than GB For 60 phase margin,, ω p2 must be greater than 1.73GB 30

31 Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero Assume that the unity-gain buffer has an output resistance of Ro It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected that another pole occurs at, 1 p4 R0 CICcCI Cc and a LHP zero at 1 z2 RC 0 c Although the LHP zero can be used for compensation, the additional pole makes this method less desirable than the following method. Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero) 31

32 Nodal Equations: VI scc gmivin scivi VI Vout R I 1 sc cr z 0 VI scc gmivi sciivout Vout VI RII 1 sccrz 0 Cc g g R R 1s R C Vout V s bs cs ds in s gmii mi mii I II z c b R C C R C C g R R C R C I I c II II c mii I II c z c c RR CC CC CC RC RC R C I II I II c I c II z c I I II II d R R C C C R I II I II c z If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots of the above transfer function can be approximated as p1 R C C R C C g R R C R C 1g R R C g R R C p I I c II II c mii I II c z c mii II I c mii II I c 2 g C g CC CC CC C p 4 mii c mii c I I II c II II 1 RC z I z 1 C c 1 1 gmii R z 32

33 Note that the zero can be placed anywhere on the real axis! We desire that z1 = p2 in terms of the previous notation 1 CII Cc CII 1 p2 z1cc Rz Rz g g C g mii mii c mii With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz). For unity-gain stability, all that is required is that A 0 A p GB g R R C p mi RC g C z I c mii II I c GB Substituting Rz into the above inequality and assuming CII >> Cc results in C g mi c CI CII gmii This procedure gives excellent stability for a fixed value of CII ( CL). Unfortunately, y asclchanges, p2 changes and the zero must be readjusted to cancel p2! 33

34 Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp p 1 1 gmi gmi g R R C g g R R C A C mii II I c mii mi II I c 0 c p 2 g C mii II g C m6 L p 4 1 z1 RC z I C c Rz g m6 6 Design of the Nulling Resistor (M8) For the zero to be on top of the second pole (p2), the following relationship must hold R z C c C II 1 C c C L 1 C c C L 1 C g C g C 2 I C W / L 1 1 c mii c m6 c D6 p ox 6 34

35 The resistor, Rz, is realized by the transistor M8 which is operating in the active region because the dc current through it is zero. Therefore, Rz, can be written as 1 1 Rz i / v C W / L V V D8 DS8 V 0 p ox 8 SG8 THP The bias circuit is designed so that voltage VA is equal to VB. As a result DS 8 Equatingq g the two expressions for Rz gives V R z R z 2I V V V V D10 GS10 THP GS8 THP pcoxw / L10 C W / L p GS11 GS6 ox 8 W / L ID10 W / L 2 8 pc I C W / L p ox 10 ox D10 W / L 10 Cc CL 1 1 C 2 I C W / L W / L 2 C I c D 6 p ox 6 8 p ox D 10 C c W / L W / L W / L D6 8 Cc CL 10 6 ID10 W ID10 W V L I L 11 D6 6 I W / L 8 c L W / L W / L / Cc C C W L

36 An Alternate Form of Nulling Resistor To cancel p2, R C C 1 1 g g C c L L z m6 m6b1 Cc gm6 gm6b Cc 2I 2I C 1 C W / L C W / L C D 6 D 6 B L p ox 6 p ox 6B c 36

37 Increasing the Magnitude of the Output Pole Nodal equations: R R2 g ds2 g ds4 gds 9 g ds6 g ds7 g sc I GV g V GV V m8 c in 1 1 m8 s8 1 1 out gm8 scc gm8scc 0 gm6v1g2sc2 Vout gm8 scc Solving l i for the transfer function Vout/Iin gives scc 1 Vout s gm6 gm8 I in s GG 1 2 C c C 2 C c g m 6 C c 2 CC s s gm G G GG gm G

38 Using the approximate method of solving for the roots of the denominator gives p p 1 6 g G G GG 1 C 2 c C2 Cc gm6cc gm6rds Cc m gm6rdscc 2 6 gm8rdsg2 gm6 gm8rds 2 p2 CC c 2 6 C2 3 g G m8 2 z 2 g C where all the various channel resistance have been assumed to equal rds and p2 is the output pole for normal Miller compensation. Result: Dominant pole is approximately the same and the output pole is increased by gmrds In addition there is a LHP zero at -gm8/scc and a RHP zero due to Cgd6 (shown dashed in the previous model) at gm6/cgd6. Roots are: m8 c 38

39 FEEDFORWARD COMPENSATION Use two parallel paths to achieve a LHP zero for lead compensation purposes s Vout s ACc ACc V 1 i s Cc CII s RIICc CII To use the LHP zero for compensation, a compromise must be observed Placing the zero below GB will lead to boosting of the loop gain that could deteriorate the phase margin Placing the zero above GB will have less influence on the leading phase caused by the zero Note that a source follower is a good candidate for the use of feedforward compensation This type of compensation is often used in source followers. The capacitor will provide a path that bypasses the transistor at high frequencies g mii 39

40 POWER SUPPLY REJECTION RATIO OF THE TWO-STAGE OP AMP What is PSRR? PSRR PSRR A A A A v dd v ss v v dd v v ss in in Method for calculating PSRR: V A V AV A V AV out dd dd v 2 dd dd v out Add Add 1 V V V V 1 A A PSRR out dd dd dd v v V dd ss PSRR PSRR Vout Vout If we connect the op amp in the unity-gain mode and input an AC signal of Vdd (Vss) in series with VDD (VSS), PSRR will be equal V dd PSRR V out Vss PSRR V out V 40

41 Negative PSRR g G sc sc V g sc V I c I 1 mi c out g sc V G sc sc sc V g sc V mii c II c II gd out ds gd ss Solving for Vout/Vss and inverting: 2 a CC c I CC I II CII Cc CC I gd7 CC c gd 7 Vss as bs c Vout gm7 GI scc CI bg C C C G C C C g g c GIGII gmiigmi Solve for approximate roots: Cc CC c I CC c II CC c II 1s 1 s ss mii mi g V g g mi gmiic c PSRR Vout G I g ds 7 C c CI Cgd 7 1 s 1 s G I g ds7 7 I c II gd II c I c mii mi 41

42 PSRR Cc CII s s 1 s 1 s 1 1 ss mii mi g V g g mi g mii GII Av 0 GB p2 Vout GI gds7 Cgd 7 Cc gds7 Cgd 7 s gmi 1s 1 s 1 s 1 g ds7 G I g ds7 GB G I Comments: DC gain has been increased by the ratio of GII to gds7 Two poles instead of one, however the pole at -gds7/cgd7 is large and can be ignored. 42

43 Positive PSRR The nodal equations: GI scc sciv1 gmi sccvout GIVdd g sc V G sc sc V g g V mii c 1 II c II out mii ds6 dd G g g g g, G g g, g g g, g g I ds 1 ds 4 ds 2 ds 4 II ds 6 ds 7 mi m 1 m 2 mii m 6 Using Cramers rule to solve for the transfer functionvout/vdd, and inverting the transfer function gives the following result 2 V ss as bs c Vout GI gds6 s Cc gmii GI gds6ci gmii gds6 43

44 a CcCI CICII CIICc b G C C G C C C g g I c II II c I c mii mi c G G g g I II mii mi We may solve for the approximate roots of numerator as PSRR Cc CC c I CC c II CC c II 1s 1 s dd mii mi g V g g mi gmiic c Vout GI gds6 g miicc 1 s Gg I ds6 Where gmii > gmi and that all transconductances are larger than the channel conductances: PSRR Cc CII s s 1 s 1 s 1 1 dd mii mi g g V g g G A 0 GB V out G I g ds 6 g miic c g ds 6 s G II A v 0 1 s 1 Gg I ds6 GB g ds6 mi mii II v p2 At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope and degrades the higher frequency PSRR + of the two-stage op amp. 44

45 Approximate Model for PSRR+ The M7 current sink causes VSG6 to act like a battery 2) Therefore, Vdd couples from the source to gate of M6 3) The path to the output t is through h any capacitance from gate to drain of M6 Conclusion: The Miller capacitor Cc couples the positive power supply ripple directly to the output. Must reduce or eliminate Cc! 45

46 Approximate Model for Negative PSRR with VBias Connected to Ground Path through the input stage is not important as long as the CMRR is high 46

47 Path through the output stage: Z out V I Z g 7 V Z out ss out m7 ss out 1 Rout Rout sc 1 sc R out out out Vout gm7rout V 1 sc R ss out out The two-stage op amp will never have good PSRR because of the Miller compensation The two-stage op amp is a very general and flexible op amp Cascoding! 47

48 Feedforward compensation without Miller Capacitor The compensation scheme used in this paper employs a feedforward path to create LHP zeros, but does not use any Miller capacitor. The dominant pole is not pushed to lower frequencies, resulting in a higher gain-bandwidth product with a fast step response. A vi g g mi 0i 0 j, i 1,2,3 g0 j pj, j 1,2 C s Av3 s Av Av Av 1 p1 Av1 Av2 Av3 p1 Hs Av1Av2 Av3 s s s s p1 p2 p1 p2 The OTA transfer function has two poles and a LHP zero created by the feedforward path. The location of the LHP zero is v1 v2 m1 m2 A A z g g 1 1 p1 Av3 C01 gm3 48

49 The second and feedforward stages can be designed such that the negative phase shift due to ω p2 is compensated by the positive phase shift of the LHP zero When the frequency of ω p2 exactly coincides with that of the LHP zero, the amplifier phase margin is 90 and the unity-gain frequency is given by GB A A A A A v1 v2 v3 v1 v2 p1 (a) Perfect pole zero cancellation (b) Pole zero mismatch This compensation scheme results in an amplifier with high gain and fast response The bandwidth improvement is due to the fact that the poles are not split, as is the case in any amplifier with Miller compensation 49