GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering


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1 NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the paper. (1 Pt.) 2. Put answers to all questions in the spaces provided on the test. (1 Pt.) 3. Show all work for full credit on questions requiring calculations. No credit will be given for answers alone, without supporting work. 4. Problems and questions are weighted as indicated. The maximum score is 100 points. 5. If you need more paper (provided in class), remove the staple from the exam and, when finished, arrange the test in order. Place the extra pages with supporting work in the test behind the page where the problem appears and indicate accordingly. Staple the entire test together so that there are no loose pages. (1 Pt.) TEST SCORE: / 100 I certify that I have neither given nor received any assistance while taking this test from anyone. (Signature) (1 Pt.) ٱ Place a check mark in the box if you observed any suspicious actions while taking this test.
2 2 Formula Sheet: Equations/Constants that you may, or may not, need are listed below: K = 50 µa/v 2 (unless otherwise stated in the problem) K n = K W/L λ = 0.01 V 1 (unless otherwise stated in the problem) V TO = 0.7 V (unless otherwise stated in the problem) γ = 0.5 V 1/2 (unless otherwise stated in the problem) 2φ F = 0.6 V (unless otherwise stated in the problem) I DTriode = (K n /2) [2(V GS V TN )V DS  V DS 2 ] I DSat = (K n /2) (V GS V TN ) 2 (1 + λv DS ) V TN = V TO + γ [sqrt(2φ F V BS ) sqrt(2φ F )] r omos 1 / (λi DS ) g mmos = sqrt[2i DS K n ] V dssat = sqrt(2i DS /K n ) g mbmos = ηg mmos η = γ 2 sqrt(2φ F V BS ) V t = kt/q 26 mv and I S = 1E15 A (unless otherwise stated in the problem) I Diode = I S [exp(v D /V t ) 1] Cj0 C j = 1  v m 0.33 m 0.5 D ψo V A = 100 V (unless otherwise stated in the problem) β F = 50 (unless otherwise stated in the problem) I CE = I S [exp(v BE /V t ) 1] [1 + V CE /V A ] r onpn = V A / I CE g mnpn = I CE /V t CMRR = A dm / A cm Z millerin = Z / (1  k) Z millerout = Z k / (k 1)
3 3 Current Source/Sink Mirrors Part A (34 Points) 1. An ideal current mirror has high / low output resistance. (2 pts) 2. An ideal current mirror has high / low input resistance. (2 pts) 3. Using the figure shown below and assuming that the collectoremitter resistance (r o ) of bipolar transistors is equivalent to the largest possible drainsource resistance (r ds ) of MOS devices (r o_ce r ds_max V A 1/λ min ) and the overdrive (V DS_sat ) of all MOSFETs is roughly 0.3V, answer the following questions. MNA MNB I bias MNC I bias 40/10 40/10 MND A B C D a) Why was MNA added to Circuit A? (4 pts) b) What is the purpose of MNC and the resistor in Circuit C? (4 pts) c) What is the purpose of MND in Circuit D? (4 pts)
4 4 MNA MNB I bias MNC I bias 40/10 40/10 MND A B C D d) Which circuit has the lowest output V min (lowest output voltage possible for which the circuit still operates properly)? (4 pts) e) Which circuit mirrors the current most accurately ( = no systematic errors ) and why? (4 pts) f) Which circuit has the worst accuracy (with respect to systematic errors only) and why? (4 pts)
5 5 4. Derive the output resistance (R out ) of the circuit illustrated below as a function of smallsignal parameters r o1, r π1, g m1, r ds2, g m2, r ds3, g m3, r ds4, g m4, etc., and assume β is infinite for the NPN transistor. (6 pts) I bias R out MN2 MN3
6 6 Differential Amplifiers Part B (48 Points) Using the foldedcascode amplifier circuit shown, answer the following questions. 1. What is the purpose of QNB? (4 pts) V DD = 10V MPB1.5 MP12 MP11 I 12.5 v 12 RPB2 10KΩ MP22 2. What is the purpose of MNB11? (4 pts) 10µA I bias v /2 id 2 1 MP21 v /2 id MPB2 V B2 v out MNB I EE MNB11 1 I What is the value of DC current I EE? (4 pts) (assume β NPN is very large) QNB1 QNB A=2um x 2um QNB11 QNB2 4. What is the value of DC current I 12? (4 pts) (assume β NPN is very large) 5. What is the value of DC current I 21? (4 pts) (assume β NPN is very large) 6. What is the value of DC voltage V B2 (V TP = 1 and k P = 20 µa/v 2 )? (4 pts)
7 7 7. What is the input commonmode voltage range (ICMR) of this circuit, as a function of constants and V BE, V T, V DS_sat, and V CE_min? MPB1 MP12 v 12 V = 10V DD.5 I 12 MP11.5 RPB2 10KΩ MP22 10µA MP21 MPB2 I bias v /2 id 2 1 v /2 id V B2 v out MNB I EE MNB11 1 I 21 2 QNB A=2um x 2um QNB1 QNB11 QNB2 V icm (6 pts) 8. What is the maximum output voltage swing of this circuit (output commonmode range OCMR), as a function of constants and V T, V DS_sat, and V CE_min? V o (6 pts)
8 8 9. Derive the differential gain to v 12 (i.e., v 12 /v id ), as a function of g m, r ds, r o, r π, etc.? (6 pts) MPB1 V DD = 10V.5 MP12 MP11 I 12.5 RPB2 10KΩ v 12 MP22 10µA MP21 MPB2 I bias v /2 id 2 1 v /2 id V B2 v out MNB I EE MNB11 1 I 21 2 QNB A=2um x 2um QNB1 QNB11 QNB2 10. Derive the gain from v 12 to output v out (i.e., v out /v 12 ), as a function of g m, r ds, r o, r π, etc.? (6 pts)
9 9 References Part C (14 Points) 1. An ideal voltage reference has high / low output resistance. (2 pts) 2. Ideally, the resistance between a voltage reference and the supply voltage is high / low. (2 pts) 3. Why does a bootstrapped reference require a startup circuit? (4 pts) Startup Ckt. 4. Given baseemitter (V BE V ref = AV BE or I ref = V BE /R) and gatesource (V GS V ref = AV GS or I ref = V GS /R) voltage derived reference circuits, the baseemitter / gatesource derived reference circuits have lower sensitivity to the supply voltage. Explain your answer below. (6 pts)
10 10 Part A. 1. High 2. Low 3.a. To eliminate basecurrent errors 3.b. To bias with a low V CE To decrease the output V min of the circuit 3.c. To increase the output resistance of the current mirror circuit 3.d. A 3.e. B There are no Early voltage errors (V CE1 = V CE2 ) and no basecurrent errors (I CN1 = ) 3.f. C Basecurrent errors exist as well as Early voltage effects (V CE1 V CE2 ) 4. R out = (I t g m2 v gs2 )r ds2 / I t = (I t g m2 [v g v s ])r ds2 / I t v g v s = v s (g m3 r ds3 + 1) = I t r o_ce (g m3 r ds3 + 1) v = v g g s m3 r ds3 MN2 R out= V t/ It R out = (I t + g m2 [I t r o_ce (g m3 r ds3 + 1)])r ds2 / I t MN3 v = I s t r oce = [1 + g m2 r o_ce (g m3 r ds3 + 1)]r ds2 r oce Part B. 1. To reduce basecurrent errors in the QNB1, QNB11, QNB2 current mirror 2. To increase the output resistance of current sink MNB11, QNB11 3. I EE = I C_QNB11 = I C_QNB1 10 µa (QNB1,QNB11 is a 1to1 current mirror) 4. I 12 = 1.5 I D_MPB1 = 15 µa (MPB1, MP12 is a 1to1.5 current mirror) 5. I 21 = I 12 I EE /2 = 10 µa 6. V B2 = V DD I C_QNB2 R PB2 V SG_MPB2 = 10 (10µ)(10k) V TP V ON_MPB2 = K ' P 2I (W / L ) = = 7.9 V
11 11 7. V CE_QNB11 + V DS_MNB11 + V BE_2 V icm V DD V SD_MP12 V CE_2 + V BE_2 where V CE_QNB11 = V BE_QNB1 + V BE_QNB V DS_sat + 3V BE V icm 10 V SD_sat V CE_min + V BE 8. V CE_2 V O V DD V SD_MP12 V SD_MP22 where V SD_MP22 I C_QNB2 R PB2 V CE_min V O 10 I C_QNB2 R PB2 V SD_min = V SD_min = 8.9 V SD_min 9. Since the emitters of 1 and 2 are acground with a differential input signal commonemitter gain configuration v 12 = (v id /2)(g m_2 )(r o_2 //r sd_mp12 //[1/g m_mp22 ]) (v id /2)(g m_2 )(1/g m_mp22 ) v 12 /v id = g m_2 /(2g m_mp22 ) 10. Commongate gain configuration v out v 12 g m_mp22 r o_2 or v out /v 12 g m_mp22 r o_2 (the resistance seen into the drain of MP22 is assumed to be much larger than r o_2 cascoded resistance sourcedegenerated circuit ) Part C. 1. Low 2. High 3. Bootstrapped references have two or more possible states of operation (e.g., on and off states). Consequently, a startup circuit is necessary to ensure the circuit operates in the desired state. 4. Baseemitter An exponentially larger change in current is required to alter V BE whereas MOSFETs require a squarelaw change to alter V GS lower output resistance.
GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
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