DEPFET sensors development for the Pixel Detector of BELLE II

Transcription

1 DEPFET sensors development for the Pixel Detector of BELLE II 13 th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD13) 7 10 October 2013, Siena, Italy Paola Avella for the DEPFET collaboration p.avella@hll.mpg.de

2 Outline SuperKEKB and BELLE II Pixel Detector (PXD) and its characteristics DEPFET technology and working principle The readout electronics Current developments: PXD6 Electrical-Multi-Chip-Module (EMCM) Summary and future plans IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 2

3 SuperKEK and BELLE II electron (7GeV) 5.0 m positron (4GeV) Nano beam scheme smaller beam size (~nm) & increased beam currents (x2) L = 8 x cm -2 s -1 (40 times larger than in KEK) E e- = 7 (8) GeV & E e+ = 4 (3.5) GeV (bg = 0.42 (KEK) 0.28 (SuperKEK)) E cm = GeV - Y(4S) Changes involving the Vertex Detector (VXD): Four layers of Double Sided Si-Strip Detector (DSSD) with a larger radius Two layers of DEPFET pixel detector (PXD) IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 3

4 The Pixel Detector (PXD) of BELLE II Fast detector to keep small occupancy High spatial resolution Very short distance from the IP Minimum thickness Radiation hardness IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 4

5 The BELLE II PXD half ladder Inner layer (L1) Outer layer (L2) # modules 8 12 Distance from IP (cm) Thickness (mm) Total # pixels x x 10 6 Pixel size (mm 2 ) 55, 60 x 50 70, 85 x 50 Sensitive area (mm 2 ) 44.8 x x 12.5 Sensor length (mm) x 250 pixels 55 x 50 mm (L1) 70 x 50 mm (L2) 512 x 250 pixels 60 x 50 mm (L1) 85 x 50 mm (L2) IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 5

6 The DEPFET working principle fully depleted bulk potential minimum for electrons the charges collected in the internal gate modulate the transistor current internal amplification g q ~ na/e - non destructive readout low power consumption the charge stored in the internal gate is removed by a reset contact Clear-gate structure used to lower the potential barrier between the internal gate and the clear 90 steps fabrication process: 9 Implantations 19 Lithographies 2 Poly-layers 2 Alu-layers 1 Copper layer Back side processing IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 6

7 The DEPFET matrix High readout speed required to keep the number of hit pixels low at each readout frame 20 ms 100 ns/electrical row The 4-fold readout is used: 4 rows are connected in parallel to gate and clear The number of drain lines increases of the same factor Three different ASICs to readout the matrix (made in radiation hard technology): SWITCHER DCD DHP IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 7

8 Steering and readout ASICs Drain Current Digitizer (DCD) Keeps the columns line potential constant Compensate for pedestal current variation Amplify the signal Shaping for noise reduction Programmable gain and BW SWITCHER Fast voltage pulses up to 20 V to activate gate rows and to clear the internal gate JTAG for interconnectivity tests 64 drivers for both gate and clear channels address 32 matrix segments 768 rows 192 electrical rows 6 ASICs needed per module Data Handling Processor (DHP) Pedestal correction Common mode correction Data reduction using the zero suppression Triggered readout scheme introduces further data reduction IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 8

9 The readout chain FLEX kapton cable 49 cm long Power Patch Panel (PPP) for power filtering and impedance matching Data Handling Hybrid (DHH) for interconnection of the half-ladder to the outside world Clock signal from the BELLE II environment Slow control master for the ASICs Multiplexing data from DHP into optical link Compute Nodes (CN) ATCA/ONSEN for tracking information from the SVD and definition of ROI within the PXD data IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 9

10 Self supporting all-silicon Ladder 3D Model of Belle-II Ladder Photo of thinned backside end-flange with CO 2 channels (blue) and capillaries for air cooling (yellow) 360 W total power consumption (18 W per ladder) 1.5 W per DCD 0.5 W per DHP 1 W for 6 SWITCHER 1 W for active area IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 10

11 Thinning technology a) oxidation and back side implant of top wafer Top Wafer c) process passivation Handle <100> Wafer open backside passivation Custom made SOI Wafer b) wafer bonding and grinding/polishing of top wafer d) anisotropic deep etching opens "windows" in handle wafer 450 mm Perforated frame Etched grooves 50 mm DEPFET thickness is hence a free adjustable parameter in BELLE II 0.2% X 0 IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 11

12 The PXD6 generation front Full size sensors for prototyping 87 small matrices for characterization 36 different designs, including flip-chip layout with ASICs mounted directly on detector 2 Al layers for routing power supplies and data signals back 8 x 6 wafers thinned up to 50 mm Pixel sizes between 50 and 200 mm Various pixel types, i.e. various gate lengths, different clear gate, enhanced drift regions IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 12

13 Laboratory tests with laser and radioactive source Trigger-less zero suppression readout with components: One Switcher-B One DCDBv2 One DHP 0.2 Small thin matrix: Belle II SD PXD6 type, 32x64 pixels, 50x75 μm 2 pitch Frame rate: 300 khz (small matrix) seed Laser scan 5x6 pixels Measurements and analysis performed by Florian Lütticke, University of Bonn g q ~ 450 pa/e - cluster Laser scan 5x6 pixels Homogeneous charge collection IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 13

14 Test DESY May 2013 PXD6 Belle II design Thin (50 μm) sensor 32x64 pixels Pitch 50x75 μm 2 SwitcherB and DCDB at full speed Belle II prototype power supply DCDB readout at 320 MHz 99% Efficiency SNR ~ Spatial resolution ~ 10 mm Cluster 3x3 g q 450 pa/e - ~ 10 μm resolution Homogeneous noise map Data analysis performed by Benjamin Schwenker, University of Goettingen and Marca Boronat, University of Barcelona IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 14

15 The Electrical-Multi-Chip-Module (EMCM) bump bonded steering and r/o ASICs 3 metal layers on periphery 4 layer kapton cable attached and wire bonded to Si-Module for I/O and power space for PXD6 DEPFET Matrix load capacitor bank for switcher test screw through Si mounting to cooling structure long drain lines connected to DCD input, more passives to emulate load of DEPFET cell, EMC tests wire bond connections to small matrix bias connections of matrix via kapton Study and characterization of routing and electronic components Understanding the technological feasibility of the 3-metal layers Practice flip-chipping and off-module interconnections IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 15

16 Present status of the EMCM SWITCHER DCD DHP TEST JIG KAPTON IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 16

17 Summary and future plans The DEPFET PXD detector promises an excellent spatial resolution of ~ 10 mm and an occupancy as low as 1%, due to a fast readout (50kHz) and a huge number of pixels (~ 8Mpix); The technology used for the production of the DEPFET PXD is extremely complex and yet fully functional; The SOI technique allows full control on the thickness of the DEPFET ladders, which have been thinned down to 75 mm (0.2% X 0 ), minimizing multiple scattering; The power consumption of each ladder is of ~ 18 W, with a major contribution coming from the steering and the readout ASICs; Considering the contribution from the readout electronics as well, the DEPFET PXD is characterized by a very high SNR of the order of 40; Study and characterization of the EMCM study of the 3-metal layers, circuitry at periphery and interconnections Test beam at DESY, January 2014 demonstration of the all-silicon module concept using PXD6 large matrices and small matrices assembled on EMCM and simultaneous testing of four DSSD layers and two PXD half ladders. IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 17

18 The DEPFET collaboration IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 18

19 Thank you! IPRD13, 7-10 October 2013, Siena, Italy Paola Avella, Max Planck Institute for Physics - Semiconductor Lab 19