An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI

Transcription

1 An On-Chip All-Digial Measuremen Circui o Characerize Phase-Locked Loop Response in 45-nm SOI Dennis Fischee, Richard DeSanis, John H. Lee AMD, Sunnyvale, California, USA MIT, Cambridge, Massachuses, USA Cusom Inegraed Circuis Conference Sepember 6, 2009

2 Ouline Moivaion Loop Measuremen Circui Algorihm Archiecure Silicon Resuls Conclusion 2

3 PLL Closed-Loop Transfer Funcion Normalized Jier Transfer (db) Frequency domain model Inpu: excess phase modulaion of inpu (reference) clock Oupu: excess phase modulaion of feedback clock refclk 2 f c PLL mod Peaking BW Low damping High damping feedback 2 f c f mod kHz MHz 0MHz 00MHz Jier Modulaion Frequency 3

4 Moivaion Sric bandwidh and peaking requiremens e.g., PCI Express Generaion 5 Gb/s 58 MHz BW / < db peaking 86 MHz BW / < 3 db peaking Lockime (funcion of BW) increasingly imporan given frequen exi from sleep/power-save saes Device PVT variaion simulaions inadequae Sandard mehods Specrum Analyzer, Waveform Generaor Problems wih sandard mehods Slow expensive Wafer? Package? Produc? inflexible 4

5 Ouline Moivaion Loop Measuremen Circui Algorihm Archiecure Silicon Resuls Conclusion 5

6 Simulaed Sep Response vs. Time Phase Error (ns) MaxOvershoo T crossover Time (µs) 6

7 T crossover (µs) Basis of Algorihm MaxOvershoo (ns) Relaionship beween ime & frequency domain behavior Lower BW higher T crossover Larger inpu phase sep larger peaking Linear Fi Linear Fi T refclk Phase Sep 2 T refclk Phase Sep % 75% 50% 75% /BW (µs) Peaking (db) 7

8 8 Closed-Form Equaions for Phase Error Damping Facor < (underdamped) Damping Facor = (criically damped) Damping Facor > (overdamped) e n sep err n e n n sep err n sinh cosh e n n sep err n sin cos Source: Gardner, Phaselock Techniques, 2005

9 T crossover (µs) Closed-Form Equaions vs. Simulaions MaxOvershoo (ns) % T refclk Phase Sep 75% T refclk Phase Sep Simulaion Equaion Simulaion Equaion /BW (µs) Peaking (db) Equaions become less accurae a high due o smoohing loop filer pole for reference spur reducion 9

10 PLL + Loop Measuremen Circui Digial Sae Machine no analog circuis Minimal overhead/inrusion communicaes wih feedback divider only Insananeously seps feedback clock phase programmable, direcional Measures T crossover and MaxOvershoo RefClk Phase- Frequency Deecor UP DN Gain Conrol Charge Pump Range Conrol Volage- Conrolled Oscillaor FbClk Feedback Divider FbCn[5:0] FbDiv[5:0] Nsep[5:0] N[5:0] Sar Loop Measuremen Circui BwCn[9:0] MaxOvershoo[5:0] BwValid 0

11 Loop Measuremen Circui Conrol Uni RefClk Sar From JTAG D Q D Q D Q D Q N[5:0]+K[5:0] Edge Deecor RefFall SarRise Edge Deecor N[5:0] FbRise BwValid En Clr En Hold D Delay D D unil unil En= Q D Q En= Hold D SepEn unil Clr= FbDiv[5:0] To Feedback Divider T crossover Deecor FbClk RefClk D Q BBPD En D Q Load_BBPD BBPD En D Q BBPD2 BwEn En BW Q Couner BwCn[9:0] To JTAG BwValid MaxOvershoo Deecor FbCn[5:0] From Feedback Divider En D Q Compare NewMaxOS SmplCn[5:0] UpdaeOS D Q RefFall MaxOvershoo[5:0] To JTAG

12 Conrol Uni RefClk RefFall Sar SarRise FbRise SepEn BwEn RefClk Sar From JTAG D Q D Q D Q D Q N[5:0]+K[5:0] Edge Deecor RefFall SarRise Edge Deecor N[5:0] FbRise BwValid En Clr En Hold D Delay D D unil unil En= Q D Q En= Hold D SepEn unil Clr= BwEn FbDiv[5:0] To Feedback Divider To T crossover Deecor 2

13 Conrol Uni and Phase Sep RefClk SepEn FbDiv[5:0] 8 8 FbCn[5:0] FbClk BwEn BwCn[9:0] RefClk Sar From JTAG D Q D Q D Q D Q N[5:0]+K[5:0] Edge Deecor RefFall SarRise Edge Deecor N[5:0] FbRise BwValid En Clr En Hold D Delay D D unil unil En= Q D Q En= Hold D SepEn unil Clr= BwEn FbDiv[5:0] To Feedback Divider To T crossover Deecor 3

14 Bandwidh/Tcrossover Tes RefClk FbClk BBPD Load_BBPD BBPD BBPD2 BwValid BwCn[5:0] From Conrol Uni Load_BBPD BwEn FbClk RefClk D Q BBPD En D Q BBPD En D Q BBPD2 En BW Q Couner BwCn[9:0] To JTAG BwValid 4

15 Peaking/MaxOvershoo Tes RefClk RefFall FbCn[5:0] SmplCn[5:0] UpdaeOS MaxOvershoo[5:0] BwValid FbCn[5:0] From Feedback Divider En D Q Compare NewMaxOS SmplCn[5:0] UpdaeOS D Q RefFall MaxOvershoo[5:0] To JTAG 5

16 Ouline Moivaion Loop Measuremen Circui Algorihm Archiecure Silicon Resuls Conclusion 6

17 Simulaions vs. Measuremens 00 MHz refclk, feedback divisor = 50 (2x25) Case R lpf (kw) I cp (µa) Simulaed Bandwidh (MHz) Par Measured Par 2 Simulaed Peaking (db) Measured Par 3 Par Par 2 Par 3 7

18 Measured T crossover vs. /BW T crossover (µs) /BW (µs) T refclk Phase Sep 50% measured 75% simulaed 75% measured

19 Measured MaxOvershoo vs. Peaking MaxOvershoo (ns) Peaking (db) T refclk Phase Sep 50% simulaed 50% measured 75% simulaed 75% measured

20 Power and Area Power (simulaed) = 2.5 mw Oupu frequency = 2.5 GHz VDD =.2 V Clocks gaed when no in use Area = 2,750 µm 2 45-nm SOI-CMOS Can easily be reduced by 4050% by replacing non-criical sense-amplifier flip-flops wih smaller maser-slave flip-flops and opimizing overshoo comparaor Layou area no a serious concern in his design 20

21 Ouline Moivaion Loop Measuremen Circui Algorihm Archiecure Silicon Resuls Conclusions 2

22 Conclusion An on-chip, all-digial sae machine can be used o accuraely esimae PLL bandwidh and peaking wih poenially large savings in eser ime. This flexible circui may be used from wafer level o produc level, minimizing die/package wase and allowing for adapive PLL loop calibraion. 22

23 Acknowledgmens Alvin Loke - AMD Gerry Talbo - AMD 23