Chapter 4. Circuit Characterization and Performance Estimation

Transcription

1 VLSI Design Chaper 4 Circui Characerizaion and Performance Esimaion Jin-Fu Li

2 Chaper 4 Circui Characerizaion and Performance Esimaion Resisance & Capaciance Esimaion Swiching Characerisics Transisor Sizing Power Analysis Oher Issues

3 Resisance Esimaion Resisance R = ( ρ / )( L / W ), where ( ρ,, L, W ) is (resisiviy, hickness, conducor lengh, conducor widh) Shee resisance =Ω/ R = R s ( L / W ) R s 1 recangular block R = R ( L / W ) s W W W L L L 4 recangular block R = R ( L / W ) R ( L / W ) s = s 3

4 Resisor None recangular (1) R=L/W L L R=L/W W W 1 W W 1 R=4L/(L+4W 1 ) L L R=L/(L+W 1 ) W W 4

5 Resisor None recangular () W 1 W 1 W W L W W W W 1 W 1 Raio=L/W Raio=W 1 /W Raio=W 1 /W W W 1 W W 1 W W 1 W 1 Raio=W /W 1 Raio=W /W 1 5

6 Capacior Load capaciance on he oupu of a CMOS gae is he sum of Gae capaciance Diffusion capaciance Rouing capaciance Capaciance can be calculaed by C ε x ε 0 = ε 0 ε d x A : dielecric consan : permiiviy of free space 6

7 Gae Capacior (1) Accumulaion Depleion gae gae V g <0 gae V gae g >0 C o ox C o Depleion layer ox Cdep P-subsrae P-subsrae 7

8 Gae Capacior () Inversion Capaciance variaion gae V gae g >0 Accumulaion Depleion Inversion 1.0 C o C dep Channel Depleion layer ox C/C o Low freq. P-subsrae High freq. 0 V V gs 8

9 Gae Capacior (3) gae C gs C gb C gd source drain C sb depleion layer subsrae C db C g =C gb +C gs +C gd 9

10 Gae Capacior (4) 10

11 Diffusion Capacior b Subsrae a Source Diffusion Area Drain Diffusion Area a b C jp X c Cd = C ja ( ab) + C jp (a + b) C ja =juncion capaciance per micron square C jp =periphery capaciance per micron C ja 11

12 Wire Capacior (1) Fringing fields W L T H subsrae Insulaor (Oxide) Muli-layer conducor C C 3 C 1 Layer 3 Layer Layer 1 C =C 1 +C 3 +C 1

13 Wire Capacior () A B C D E F G C m C m poly C m m1 C m m1 poly C C m m m1 C C Thin-oxide/diffusion Subsrae 13

14 Inducor For bond wire inducance L = µ 4h ln( ) π d For on-chip meal wires µ 8h w L = ln( + ) π w 4h The inducance produces Ldi/d noise especially for ground bouncing noise. Noe ha when CMOS circui are clocked, he curren flow changes grealy. V = L di d 14

15 Wire RC Effecs (1) I j-1 I j R R V j-1 R V R j V j+1 R C C C C C dvj ( Vj 1 V j ) ( Vj V j+ 1) CdV = Id C = ( I j 1 I j ) = d R R dv d V rc kx d = x dx = r : resisance per uni lengh c : capaciance per uni lengh 15

16 Wire RC Effecs () 1mm 1mm inpu buffer buf oupu Assume ha x = x Wih buffer p = buf = 4ns + + 4ns = 8ns buf buf 1000 Wihou buffer 15 p = = 16ns 16

17 Delay Analysis (1) V in () V ou () V ds =V gs -V C L V DD I ds V in () V DD V ou () pf 90% 50% dr V ou () V DD f 10% r 17

18 Delay Analysis () P-device V ou () P-device V ou () N-device I dsn C L N-device R cn C L Sauraed V ou >=V DD -V n Nonsauraed 0<V ou <=V DD -V n P-device I dsp P-device R cp V ou () V ou () N-device C L N-device C L Sauraed V ou <= V p Nonsauraed V p <V ou <V DD 18

19 Delay Analysis (3) The fall ime consiss of wo inervals: f1 =period during which he capacior volage, V ou, drops from 0.9V DD o (V DD -V n ) f =period during which he capacior volage, V ou, drops from (V DD -V n ) o 0.1V DD C L f dv d ou k βn + ( VDD Vn) CL r k β V n DD = 0 C β V p L (In sauraion) DD p k C V L DD 1 ( β + n 1 β p ) 19

20 Design Challenges Reduce C L Careful layou can help o reduce he diffusion and inerconnec capaciance Increase β n and β p Increase he ransisor sizes also increases he diffusion capaciance as well as he gae capaciance. The laer will increase he fan-ou facor of he driving gae and adversely affec is speed. Increase V DD The designer does no have oo much conrol over his facor, as he supply volage is deermined by sysem and echnology consideraions. 0

21 Gae Delays IN-3 IN- IN-1 P 3 P P 1 N 3 N N 1 β = neff ou (1/ βn 1) + (1/ β n) + (1/ β n3) β = β = β β = n1 n n3 1 neff β 3 n L L 3L L 1

22 Delay Analysis Swich Level RC Model A B P 4 P 3 P P 1 ou N 4 C ab C ou N 3 R p C N C bc R n C ou D N 1 C cd

23 Swich Level RC Model Simple RC model df dr = Rpulldown C pulldown pah = ( R + R + R + R ) 4 ( C + C + C + C N1 N N 3 N ou ab bc cd = Rp 4 Cou Elmore delay model = R C d df i i i ( RN1 Ccd ) + [( RN1 + RN ) Cbc ] + [( RN1 + RN + RN 3) Cab = + [( R + R + R + R ) 4 C N1 N N 3 N ou ] ) ] 3

24 Transisor Sizing inv-pair 4/1 R I charge R /1 3C eq I discharge 3C eq W p =W n R inv pair = fall + rise = R3 Ceq + 3C = 3 RC + 3 eq RC eq eq = 6RC eq C eq is he capaciance of a uni (/1) NMOS ransisor R is he equivalen channel resisance of a uni NMOS 4

25 Transisor Sizing inv-pair /1 R I charge R /1 C eq I discharge C eq W p =W n = + = R C + RC inv pair fall rise eq eq = 6RC eq 5

26 Transisor Sizing /3 3R p I charge R /1 C eq I discharge C eq inv pair = rise + fall = 6R( Cg + Cd ) + R( Cg + Cd ) = 7RC eq C = C + C eq g d 6

27 Transisor Sizing 1 a a a 3 n(4) sages C L a/ln(a)e Sage raio -- a 7

28 Power Dissipaion Insananeous power: p() = v()i() = V supply i() Peak power: P peak = V supply i peak Average power: 1 P ave = ) T V + T supply + T p( d = T i supply ( ) d 8

29 Power Analysis Power consumpion of a CMOS circui Saic power caused by he leakage curren and oher saic curren Dynamic power caused by he oal oupu capaciance Dynamic power caused by he shor-circui curren Toal power consumpion of a CMOS circui is given by P = P + P + s d P sc 9

30 Power Analysis Saic Power Gnd V in V ou V DD p + n + n + p + p + n + n-well p-subsrae PN juncion reverse bias leakage curren i qv / KT 0 = is( e 1) P s = n 1 I leakage V sup ply 30

31 Power Analysis Dynamic Power Le he inverer is operaed a a swiching frequency f=1/t V DD i p V in i V o ou C L P i i d p n 1 T = io ( ) vo( ) d T 0 dvo = io = CL d dvo = io = CL d i n P d = 1 T [ V 0 DD C L v o dv o 0 V DD C L v o dv o ] C V T L DD P d = = fc L V DD 31

32 Energy vs. Power Energy consumpion of an inverer (from 0 V DD ) The energy drawn from he power supply is E = QV = The energy sored in he load capaciance is DD Ecap Cv 0 odvo = C LVDD V DD 0 The E cap is consumed by he pull-down NMOS = The oupu from V C V L DD 1 Low-energy design is more imporan han lowpower design 3

33 Power Analysis Shor-Circui Power V DD T V DD - V p r f V in i sc V ou V n C L I max I mean 1 3 P I I sc mean mean = I mean = 4 = [ T V 1 [ T DD 1 1 i ( ) d i ( ) d ] + 3 i ( ) d ] 33

34 Power Analysis Shor-Circui Power I V 1 P mean in sc = [ T V DD ( ) = = V V T DD r = β = 1 4 r r ( V 1 DD β ( V in V T ( ) ) 3 τf V T ) d ] τ = =, where r f 34

35 Power Analysis Swiching Aciviy The dynamic power for a complex gae canno be esimaed by he simple expression C L V DD f Dynamic power dissipaion in a complex gae Inernal cell power V DD Capaciive load power Capaciive load power P = α C V f Inernal cell power P L in = n i = 1 L α i DD C i V V i DD f B A A C C B C 1 C ou 35

36 Power Analysis Gliching power In a saic logic gae, he oupu or inernal nodes can swich before he correc logic value is being sable. This phenomenon resuls in spurious ransiions called gliches. ABC A B C D Z D Z Uni delay Spurious ransiion 36

37 Rules for avoiding Gliching power Balance delay pahs; paricularly on highly loaded nodes Inser, if possible, buffers o equalize he fas pah Avoid if possible he cascaded implemenaion Redesign he logic when he power due o he gliches is an imporan componen 37

38 Principles for Power Reducion Prime choice: reduce volage Recen years have seen an acceleraion in supply volage reducion Design a very low volage sill open quesion (0.6V 0.9V by 010) Reduce swiching aciviy Reduce physical capaciance 38

39 Low-Power Design Layou Guidelines Idenify, in your circui, he high swiching nodes Use for hese high aciviy nodes low-capaciance layers such as meal, meal3, ec. Keep he wires of high aciviy nodes shor Use low-capaciance layers for high capaciive nodes and busses 39

40 Low-Power Design Guidelines Avoid, if possible, he use of dynamic logic design syle For any logic design, reduce he swiching aciviy, by logic reordering and balanced delays hrough gae ree o avoid gliching problem In non-criical pahs, use minimum size devices whenever i is possible wihou degrading he overall performance requiremens If pass-ransisor logic syle is used, careful design should be considered 40

41 Charge Sharing Charge Q=CV A bus can be modeled as a capacior C b If he volage on he bus is sampled o deermine he sae of a given signal Bus V b C b V s C s ( Q = C Vb) Q = C V ) b b ( s s s Q = C V + C T T b b b C = C + C s s V s QT V R = = ( CbVb + CsVs ) /( Cb + Cs) C T 41

42 Conac Replicaion Curren ends o concenrae around he perimeer in a conac hole This effec, called curren crowding, pus a pracical upper limi on he size of he conac When a conac or a via beween differen layers is necessary, make sure o maximize he conac perimeer (no area) 4

43 Ground Bounce Volage V in Curren V ou Time L V DD Pad I Time V in I V ou V SS Pad V L Time L V L =L(di/d) Ground bounce 43

44 Approaches for Coping wih L(di/d) Muliple power and ground pins Resric he number of I/O drivers conneced o a single supply pins (reduce he di/d per supply pin) Careful selecion of he posiion of he power and ground pins on he package Avoid locaing he power and ground pins a he corners of he package (reduce he L) Increase he rise and fall imes Reduce he di/d Adding decoupling capaciances on he board Separae he bonding-wire inducance from he inducance of he board inerconnec 44

45 Package Issues Packaging requiremens Elecrical: low parasiics Mechanical: reliable and robus Thermal: efficien hea removal Economical: cheap 45

46 Bounding Techniques Wire Bonding Subsrae Die Pad Lead Frame 46

47 Die Cos Single die Wafer Going up o 1 (30cm) 47

48 Yield Esimaion Dies No. of good chips per wafer Y = 100% Toal number of chips per wafer Die cos = π per wafer = Wafer cos Dies per wafer Die yield ( wafer diameer/) die area π wafer diameer die area 48