Digital Integrated Circuits

Transcription

1 Digial Inegraed ircuis YuZhuo Fu Office locaion:47 room WeiDianZi building,no 800 Donghuan road,minhang amus Inroducion Digial I

2 3.MOS Inverer Inroducion Digial I

3 ouline MOS a a glance MOS saic behavior MOS dynamic behavior Power, Energy, and Energy Delay Persecive ech. Digial I 3

4 omuing i more simle by esimaion Inroducion Digial I Slide 4

5 Effecive Resisance Shockley models have limied value No accurae enough for modern ransisors Too comlicaed for much hand analysis Simlificaion: rea ransisor as resisor Relace I ds ( ds, gs ) wih effecive resisance R I ds = ds /R R averaged across swiching of digial gae Too inaccurae o redic curren a any given ime Bu good enough o redic R delay Digial I Slide 5

6 R Delay Model Use equivalen circuis for MOS ransisors Ideal swich + caaciance and ON resisance Uni nmos has resisance R, caaciance Uni MOS has resisance R, caaciance aaciance roorional o widh Resisance inversely roorional o widh g d k s g d R/k k s k k g d k s g s k R/k k k d Digial I Slide 6

7 Reason of R I DSAT = k ' W ( GT DSAT - DSAT ) Digial I Slide 7

8 R alues aaciance = g = s = d = ff/mm of gae widh alues similar across many rocesses Resisance R 6 KW*mm in 0.6um rocess Imroves wih shorer channel lenghs Uni ransisors May refer o minimum conaced device (4/ l) Or maybe mm wide device Doesn maer as long as you are consisen Digial I Slide 8

9 Inverer Delay Esimae Esimae he delay of a fanou-of- inverer A Y Digial I Slide 9

10 Inverer Delay Esimae Esimae he delay of a fanou-of- inverer R A Y R Y Digial I Slide 0

11 Inverer Delay Esimae Esimae he delay of a fanou-of- inverer R A Y R Y R Digial I Slide

12 Inverer Delay Esimae Esimae he delay of a fanou-of- inverer R A Y R Y R d = 6R Digial I Slide

13 MOS dynamic characerisic MOS caaciances mosaic MOS roagaion delay Oimizing inverer sizing Digial I 3

14 ircui Under Design DD DD M M4 in ou ou M M3 This wo-inverer circui will be manufacured in a win-well rocess. Digial I 4

15 MOS Inverer: Transien Resonse DD H = f(r on. ) = 0.69 R on ou ou ln(0.5) R on DD in = DD R on Digial I 5

16 MOS caaciance mosaic Wire caaciance Juncion(diffusion) caaciance Gae caaciance Mos of hem are nonlinear funcions! Digial I 6

17 omuing he aaciances DD DD PMOS DD in gd M db ou g4 M4 ou In. mm =l Ou Meal M db w Inerconnec g3 M3 Polysilicon Fanou NMOS GND Simlified Model in ou Digial I 7

18 aaciance model GS GD GB SB GSO GDO GB Sdiff GS GD S GS G GD D DB Ddiff SB GB DB B Digial I 8

19 The Miller Effec D gd ou ou D in D gd M D in M A caacior exeriencing idenical bu oosie volage swings a boh is erminals can be relaced by a caacior o ground, whose value is wo imes he original value. Digial I 9

20 Miller effec Z I in in Z ou in Av Z in Z in I in in in Zin A v in Z A v in Z in ou Z s in ou Z in s( A ) s ( ) M Av v M Digial I 0

21 Digial I Diffusion caaciances Slide m D j D j j d dq Φ ) ( ) ( j eq low high low j high j D j eq K Q Q Q D D 0-0 m Φ Φ Φ Φ j m D m D D A D A si D D D A D A si D j m N N N N q A m N N N N q A Q m D A D A si D D A D A si D j N N N N q A N N N N q A Φ Φ 0 m low m high low high m eq m K ) ( ) ( ) )( (

22 omuing he aaciances NMOS and PMOS almos is same for uni caaciance J JSW ox (ff/um ) o (ff/um) j (ff/um ) m j Φ b () jsw (ff/um) m jsw NMOS PMOS DG0 W/ AD(um ) PD(um) AS(um ) PS(um) NMOS 3/ PMOS 9/ Φbsw () Digial I

23 omuing he aaciances PMOS DD AD=4*4+3*=6+3=9λ PD= =5λ In Ou. mm =l Meal Polysilicon NMOS GND Digial I Slide 3

24 omuing he aaciances high=-.5,low=-.5[nmos,{.5->.5} H] Boom lae:keqn(m=0.5,φ0=0.9)=0.57 Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.6 low=0,high=-.5 [NMOS,{0->.5}H] Boom lae:keqn(m=0.5,φ0=0.9)=0.79 Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.8 high=-.5,low=0 [PMOS,{.5->.5}H] Boom lae:keq(m=0.48,φ0=0.9)=0.79 Sidewall:Keqw(m=0.3,Φ0=0.9)=0.86 high=-.5,low=-.5 [PMOS,{0->.5}H] Boom lae:keq(m=0.48,φ0=0.9)=0.59 Sidewall:Keqw(m=0.3,Φ0=0.9)=0.7 Digial I 4

25 omuing he aaciances caacior exression alue(ff) (H->) gd GD0 n*wn gd GD0 *W db KeqnADn J +KeqwnPDn JSW db KeqnADn J +KeqwnPDn JSW.5.5 g3 ( GD0 n+ GSO n)wn+oxwnn g4 ( GD0 + GSO )W+oxW.8.8 w alue(ff) (->H) Digial I 5

26 MOS dynamic characerisic MOS caaciances mosaic MOS roagaion delay Oimizing inverer sizing Digial I 6

27 Proagaion delay: firs order analysis Proagaion delay model of R R I eq sa O OH v OH / O v v dv 3 DD 7 ( - l v - v I ( l ) 4I 9 ( W v ' ) n kn sa DSAT n ( DD - T n - DSAT n DSAT Assuming ransisor as sauraion n ) DD ) Digial I 7

28 Digial I 8 Proagaion delay: firs order analysis Proagaion delay model of R DSAT DD eq H I R ) - ( 4 3 * 0.69 ) ln( DD l DSATn DD eqn H I R ) - ( 4 3 * 0.69 ) ln( DD l ) /) - ( '* * /) - ( '* * ( 0.5* )* *( * 0.69*0.75/ 0.69* n n n n DSAT GT DSAT DSAT GT DSAT n n DD dsa dsan DD eq eqn H H k W k W I I R R

29 Inverer Transien Resonse H f in H (sec) x 0-0 From simulaion: H = 39.9 sec and H = 3.7 sec r DD =.5 0.5mm W/ n =.5 W/ = 4.5 R eqn = 3 kw (.5) R eq = 3 kw ( 4.5) H = 36 sec H = 9 sec So = 3.5 sec Digial I

30 Inverer Proagaion Delay, Revisied To see how a designer can oimize he delay of a gae have o exand he R eq in he delay equaion H = 0.69 R eqn = 0.69 (3/4 ( DD )/I DSATn ) DD () 0.5 / (W/ n k n DSATn ) Digial I

31 Design echniques for minimized roagaion delay Reduce Kee he drain diffusion areas as small as ossible Increase he W/ raio of he ransisor Increase dd H ( W ) n k 0.5* ' n DSAT n ( l DD ) Digial I 3

32 Design for Performance Reduce inernal diffusion caaciance of he gae iself kee he drain diffusion as small as ossible inerconnec caaciance fanou Increase DD can rade-off energy for erformance increasing DD above a cerain level yields only very minimal imrovemens Increase W/ raio of he ransisor he mos owerful and effecive erformance oimizaion ool in he hands of he designer wach ou for self-loading! when he inrinsic caaciance dominaes he exrinsic load Digial I

33 Define NMOS-o-PMOS raio H H ln( ) R eq n ln( ) R eq ( W ) ( W ) ' n kn ' k DSAT n In order o creae an inverer wih a symmerical roagae delays Also creae symmerical T DSAT (W ) (W ) n = R eq k n ' DSATn ( M - Tn - DSAT n ) k ' DSAT ( DD - M + T + DSAT ) R eq n ( W ) ( W ) ' n ' DSAT β =.4 which Rn=R! n k k DSAT n Digial I 34

34 Which oin is oimal delay? 5 x H H H ln( ) R eq ( W ) ' k DSAT (sec) 4 H ln( ) R eq n ( W ) ' n kn DSAT n b W /W n Assume = Digial I 35

35 Which oin is oimal delay? ( W b d n ) d ( W ) n g n DD g w ( b )( d n gn DD ) w in gd M db ou g4 M4 ou M db w Inerconnec g3 M3 H H 0.345(( b )( ln d n (( b )( g n ) d w n ) R eq n g n ( ) ) b )( R Digial I 36 w eq n R eq b )

36 Which oin is oimal delay? 0 b [ 0.345(( b )( d n gn b ) w ) R eq n ( )] b 0 b ( dn w gn ) 3 3 dd.5 0.5um.54 This r is differen from before! I is he resisor rae of he NMOS and PMOS Digial I 37

37 Summary of raio Bea=.6, we have minimum delay Bea=.4, we have equal delay hl = lh Bea=3.5, we have M = dd / Digial I 38

38 MOS dynamic characerisic MOS caaciances mosaic MOS roagaion delay Oimizing inverer sizing Digial I 39

39 Increasing inverer erformance by sizing he NMOS and PMOS 0.69R 0.69( R 0.69 ref eq ( in S)( S iref ex S ) )( ex iref 0.69R ex eq S in iref ( ) If load ex in ) If no load S>>0 will eliminae he imac of any exernal load Inrinsic delay is indeenden of he sizing of he gae Digial I 40

40 Device Sizing 3.8 x (for fixed load) 3.4 (sec) Examle 5.5 Self-loading effec: Inrinsic caaciances dominae S Digial I 4

41 Digial I 4 Inverer hain If is given: - How many sages are needed o minimize he delay? - How o size he inverers? In Ou ) ( ) ( ) ( 0.69 ) (

42 Delay Formula Delay ~ R W in kr W in / f / in 0 in = gin wih f = / gin - effecive fanou R = R uni /W ; in =W uni 0 = 0.69R uni uni Digial I 43

43 Aly o Inverer hain In Ou N = N j ~ R uni uni gin, j gin, N i N gin, j j, 0, gin, N j gin, j j Digial I 44

44 Oimal Taering for Given N Delay equaion has N - unknowns, gin, gin,n Minimize he delay, find N - arial derivaives Resul: gin,j+ / gin,j = gin,j / gin,j- Size of each sage is he geomeric mean of wo neighbors gin, j gin, j gin, j each sage has he same effecive fanou ( ou / in ) each sage has he same delay Digial I 45

45 Oimum size for fixed Number of Sages When each sage is sized by f and has same eff. fanou f: Effecive fanou of each sage: f N F f N F / gin, Minimum ah delay N 0 N F / Digial I 46

46 Examle In f f Ou = 8 / has o be evenly disribued across N = 3 sages: f 3 8 / has o be evenly disribued across N = 4 sages: f 4 8? Digial I 47

47 Oimum Number of Sages For a given load, and given inu caaciance in Find oimal sizing f N ln F ln f / N F / f 0 0 f F 0 ln in F f ln N f in wih ln f N f ln ln 0 F f f e f Digial I 48

48 Oimum Effecive Fanou f Oimum f for given rocess defined by f e f f o = 3.6[4] for = For = 0, f = e, N = lnf Digial I 49

49 Imac of Self-oading on No Self-oading, =0 Wih Self-oading = u/ln(u) 40.0 x=0,000 x= x=00 x= u Digial I 50

50 Normalized delay funcion of F f = N F, N = ln F ln f = ln F ln 3.6 = 0.78ln F = N 0 ( ) N + F / γ = 0.78ln F(+3.6) = 3.6ln F F unbuffered Two sages Inverer chain Digial I 5

51 Buffer Design N f Digial I 5

52 More general examle = N0 ( ) + f / γ 4 F = f = 4 = 3 4 = 6 3 = 3 3 = f 3 = in 3 3 ou 3 = 6 3 f 3 = f = = = 4 f 3 = 4* = 3 6 Digial I Slide 53

53 Inu Signal Rise/Fall Time In realiy, he inu signal changes gradually (and boh PMOS and NMOS conduc for a brief ime). This affecs he curren available for charging/discharging and imacs roagaion delay. increases linearly wih increasing inu sloe, s, once s > s is due o he limied driving caabiliy of he receding gae x 0 - s (sec) for a minimum-size inverer wih a fanou of a single gae x 0 - Digial I

54 Design hallenge A gae is never designed in isolaion: is erformance is affeced by boh he fan-ou and he driving srengh of he gae(s) feeding is inus. i = Digial I ( 0.5) Kee signal rise imes smaller han or equal o he gae roagaion delays good for erformance good for ower consumion i se + η Keeing rise and fall imes of he signals small and of arox. equal values is one of he major challenges in high-erformance designs(sloe engineering.) i- se

55 Rising-fall ime of he inu signal i = i se + η i- se Noe: increases linearly wih increasing inu sloe,once s > ( s =0) in ou 3 Digial I Slide 56

56 Process orners Process corners describe wors case variaions If a design works in all corners, i will robably work for any variaion. Describe corner wih four leers (T, F, S) nmos seed MOS seed olage Temeraure Digial I Slide 57

57 Imoran orners Some criical simulaion corners include Purose nmos MOS DD Tem ycle ime Power Subhrehold leakage Pseudo-nMOS Digial I Slide 58

58 Imoran orners Some criical simulaion corners include Purose nmos MOS DD Tem ycle ime S S S S Power F F F F Subhrehold F F F S leakage Pseudo-nMOS S F?? 5: Nonideal Transisors Slide 59 Digial I