CLOSED FORM SOLUTION FOR DELAY AND POWER FOR A CMOS INVERTER DRIVING RLC INTERCONNECT UNDER STEP INPUT

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1 Journal of Elecron Devices, ol. 0, 0, pp JED [ISSN: ] CLOSED FORM SOLUTION FOR DELAY AND POWER FOR A CMOS INERTER DRIING RLC INTERCONNECT UNDER STEP INPUT Susmia Sahoo, Madhumani Daa, Rajib Kar Deparmen of Elecronics and Communicaion Engineering Naional Insiue of Technology, Durgapur, Wes Bengal, INDIA rajibkarece@gmail.com Received /06/0, online 8/06/0 Absrac In his paper, a closed form delay and power model of a CMOS inverer driving a resisive-inducive-capaciive load is presened. The model is derived from Sakurai s alpha-power law and exhibis good accuracy. The model can be used for he design and analysis of he CMOS inverers ha drive a large inerconnec RLC load when considering boh speed and power. Closed form expressions are also presened for he propagaion delay and ransiion ime which exhibi less han 5% error compared o he SPICE for a wide range of RLC loads. Explici mehods are also provided for modelling he shor-circui power dissipaion of a CMOS inverer driving a RLC line. The average error is wihin % compared o SPICE for mos pracical loads. The resisive power dissipaion has also been considered for various RLC loads which are accurae o wihin 9% o ha of SPICE. Keywords: On-Chip; Delay; Power; RLC Inerconnec; LSI I. INTRODUCTION As he die size of CMOS inegraed circuis coninue o decrease, inerconnecions have become increasingly significan []. Wih a linear increase in lengh, inerconnec delay increases quadraically due o he linear increase in boh inerconnec resisance and capaciance []. Large inerconnec loads no only affecs he performance bu also cause excessive power dissipaion. A large load degrades he shape of pu waveform; dissipae excessive shor circui power in he following sages loading a CMOS logic gae. Several mehods have been inroduced o reduce inerconnec delay so ha hese impedances don dominae he delay in he criical pah [-7]. Furhermore, wih he inroducion of porable compuers, power has become an imporan facor in he circui design process. Thus, power consumpion mus be accuraely esimaed for improving circui speed when driving long inerconnecions. Therefore, circui level models describing boh dynamic power and, recenly, shor-circui power have become increasingly imporan [8-]. In his paper, an analyical expression for he ransien response of a CMOS inverer driving a lumped RLC load is presened. This approach is differen from [-3], where a lumped lossless capaciive load is considered. The proposed mehod is he exension of [5] where, a lumped RC load is considered. Furhermore, Sakurai s alpha power law [4] is used o describe he circui operaion of he CMOS ransisors raher han he classical Shichman-Hodges model [6]. The alpha power law model considers shor channel behaviour, permiing increased accuracy and generaliy in he delay and power expressions. These expressions are used o esimae he propagaion delay and rise and fall imes (or ransiion ime) of a CMOS inverer. Since he pu waveform is accuraely calculaed, he shor-circui power [7] dissipaed by he following sage can also be esimaed. Furhermore, due o is simpliciy, hese expressions permi linear programming echniques o be used when opimizing he placemen of buffers for boh speed and power. Delay and power expressions for on-chip RC inerconnec have been proposed in [9]. In [0], he auhors have proposed a delay and power formula using 4 model. Bu he model is compuaionally complex. A number of delay models [-3], and power models [4] have been proposed for RC inerconnec. Bu wih he increase in he frequency of operaion and he wire sizes, he inducance play an imporan role in deermining he performance of on-chip inerconnecs. In order o overcome hese problems, his paper models he on-chip inerconnec as disribued RLC segmens. This paper is organized as follows: Secion discusses he proposed delay model of a CMOS inverer driving a RLC load. Secion 3 presens he power esimaion echniques of he same inverer circui. Secion 4 shows he simulaion resuls and finally secion 5 concludes he paper. II. PROPOSED DELAY MODEL OF A CMOS INERTER DRIING RLC LOAD An analyical expression describing he behaviour of a CMOS inverer driving a lumped RLC load based on Sakurai s alpha-power law model [4] is presened. The corresponding circui schemaic is given in Figure.

2 S. Sahoo e al, Journal of Elecron Devices, ol. 0, 0, pp process dependen consan, and α models he degree by which velociy sauraion affecs he drain o source curren., where, α= corresponds o a device operaing srongly under velociy sauraion, while α= represens a device wih negligible velociy sauraion. DD is he supply volage, and T is he MOS hreshold volage (where TN ( TP ) is he N- channel (P-channel) hreshold volage). Assuming a uni sep inpu is applied o he circui shown in Figure, can be derived from (). The linear equaion, wrien in Laplace form is, Figure. A CMOS Inverer Driving a RLC load The alpha-power law model accuraely describes he effecs of shor-channel behaviour, such as velociy sauraion, while providing a racable soluion. The linear region form of alphapower model is used o characerize he I- behaviour of he ON ransisor, since a large porion of he circui operaion occurs wihin his region under he assumpion of a sep or a fas ramp inpu signal. When he inpu o he inverer is a uni sep or a fas ramp, is iniially larger han ( GS - T ) for a shor period of ime han for he case of a slow ramp. Therefore, he circui operaes in linear region for a greaer porion of he oal ransiion ime for a large RLC inerconnec load. When he load resisance is large, a large IR volage drop occurs across he load resisor once he capacior begins o discharge, hus DS is nearly immediaely less han ( GS - T ). The N-channel device operaes in he linear region once he sep inpu goes high. However, if he inpu waveform increases more slowly or he load impedance is small, he inverer operaes in sauraion region for longer ime period before swiching o he linear region. Only he falling pu (rising inpu) waveform has been considered in his paper. The following analysis, however, is equally applicable o a rising pu (falling inpu) waveform. The lumped load is modelled as a resisor in series wih an inducor and a capacior. The curren hrough he pu load capaciance is of same magniude and of opposie polariy o ha of he N-channel drain curren (he P-channel curren is ignored under he assumpion of he sep or fas ramp inpu). The capaciive curren is, ic d C id d () Where, C is he pu capaciance, is he volage across he capaciance C, ic is he curren discharged from he capacior, and i d is he drain curren hrough he N-channel device. From α power law, The N-channel linear drain curren is given by [4], d I d GS 0 T C DS GS T d do DD ;, T DS GS I d0 represens he driver curren of he MOS device and is proporional o W/L, d0 represens he drain-o-source volage a which velociy sauraion occurs wih, and is a GS T DD () Cs s C or, s LC LC Where, (0) s RC (0) RC Id0 d0 d0 Equaion (3) yields, sc (0) C RI c (0) is he sauraion conducance. e ( ) (0) e (4) Where,,,, L and 4 LC R LsI c (3) Graphs of () for a wide range of resisive, inducive and capaciive values are shown in Figure 3. I shows ha he analyical expression of pu volage as given in (4) closely approximaes he SPICE resul for mos of he region of operaion for a wide range of load impedances. From (4), he propagaion delay of a CMOS inverer can be calculaed as, (0) ln ln ( ) For 50% delay, (5) ln (6) PD The ransiion ime of a CMOS inverer driving a lumped RLC load calculaed a he 90% poin r is, ln.3 (7) r Addiional delay expressions ha are used for deermining shor circui power are, ln ln TN DD TN (8) ln ln DD TP DD TP (9) 465

3 S. Sahoo e al, Journal of Elecron Devices, ol. 0, 0, pp Equaions (8) and (9) describe he ime for he pu volage o change by a hreshold volage from eiher ground or DD for an N-channel or P-channel device, respecively. III. PROPOSED POWER ESTIMATION TECHNIQUE Power consumpion has become one of he premier issues in LSI circui design. There are wo primary conribuions o he oal ransien power dissipaed by a CMOS inverer, dynamic power and shor-circui power dissipaion [8-], [7-8]. The shor-circui power is ofen negleced, and he dynamic power is assumed o be dominan. As described below and in [8-], [7-8], he magniude of he shor-circui power is load dependen, and i is shown in his paper ha shorcircui power can be a significan porion of he oal ransien power dissipaion. III. Dynamic Power Dynamic power is he energy required o charge and discharge a load capaciance C and is characerized by, C f ; where is he source volage and f is he swiching frequency. The dynamic power is independen of he load resisance. III..Shor Circui Power This paper presens a closed form expression for modelling he shor circui power in a CMOS inverer driving RLC inerconnecs. The logic sage following a large RLC load may dissipae significan amoun of shor-circui power due o he degraded waveform originaing from he CMOS inverer driving a RLC load (Figure ). In he region where he inpu signal is swiching beween TN and ( DD + TP ), a DC curren pah exiss beween DD and ground. The excess curren dissipaed during his region is called he shor-circui curren [7]. Shor-circui curren occurs due o a slow inpu ransiion, and for a balanced inverer, he peak curren occurs near he middle of he inpu ransiion. An example of shor-circui curren is shown by he solid line in he lower graph of Fig. 4. The oal shor-circui curren I SC can be esimaed by approximaed I SC as a riangle. Therefore, he inegral of I SC is he area of a riangle, base heigh. In erms of he shorcircui curren, he heigh can be modelled as I peak and he base can be modelled as base (Figure 4). I peak is he maximum sauraion curren of he load ransisor and depends on boh GS and DS, herefore, I peak is boh inpu waveform and load dependen. base is he ime during which boh N- channel and P-channel ransisors are urned on, permiing a DC curren pah o exis beween DD and ground. This ime occurs over he region, TN in DD TP. Therefore, base is found from he difference beween (8) and (9),. TP TN The area defined by his riangle is base heigh models he oal shor-circui curren I SC sourced by a CMOS inverer due o a non-sep inpu []. DD The oal shor-circui curren muliplied by f and is he shor-circui power. The shor-circui power dissipaion PSC of he following sage for one ransiion (eiher rising or falling edge) can, herefore, be approximaed by, PSC base heigh DD f (0) Subracing (8) from (9) forms he logarihmic quoien, ln TN base DD TP. By insering his expression for base ino (0), he shor-circui power dissipaion PSC of a CMOS inverer following a lumped RLC load over boh he rising and falling ransiions can be calculaed as, PSC TN ln I peak fdd DD TP () Figure. Non-Sep Inpu Driving CMOS Inverer Sage Creaes Shor Circui Power III.3 Resisive Power Dissipaion In resisive inerconnec, power is no only dissipaed due o charging and discharging he load capaciance, bu also by he load resisance. This power dissipaion can be quanified by f i R, where, i is he curren hrough he load resisance. The idenical curren ha is discharged by he load capacior flows hrough he resisor. This capaciive curren is d I C C. Therefore, by aking he derivaive of (4), he d insananeous curren hrough a resisive load i R () is given by, i R C e ( ) (0) e () The average resisive power is given by, P R frc e (0) e d (3) 0 Inegraion (3), we ge, e e (4) P R frc (0) e I SIMULATION RESULTS AND DISCUSSIONS The accuracy of he analyic delay model as compared o he SPICE is abulaed in Table and for a wide variey of pu load resisances, inducances and capaciances. Table I represens ransiion ime and propagaion delay ime of a 466

4 S. Sahoo e al, Journal of Elecron Devices, ol. 0, 0, pp CMOS inverer driving RLC load for various R and C values for L=nH. The average error of he ransiion ime r as compared wih SPICE is 6.4%, and he average error of he propagaion delay, PD, as compared wih SPICE is.58%. Table represens ransiion ime and propagaion delay ime of a CMOS inverer driving RLC load for various R and L values for C=pF. The average error of he ransiion ime r as compared o SPICE is.38%, and he average error of he propagaion delay PD as compared o SPICE is 3.7%. As noed above, (6) and (7) can be used o esimae he propagaion delay and ransiion ime of a CMOS inverer driving a RLC inerconnecs line. Since he shape of he pu waveform is now known, (8) and (9) can also be used wih (7) o esimae he shor-circui power dissipaion of a CMOS gae loading he high impendence inerconnec line, as discussed in Secion 3. The shor-circui power derived from () for a wide variey of RLC loads beween he CMOS inverer sages as shown in Figure is compared wih SPICE and given in Table 3 and 4. Table 3 shows he shor circui power dissipaed by inverer circui for various R and C values for consan L. The resul is compared wih SPICE and he average error is.7%. Table 4 presens shor circui power dissipaed by inverer circui for various R and L values for C=fF. The resul is compared wih SPICE value and average error is 0.%. For smaller RLC loads, hence faser ransiion imes, here is negligible shor-circui power since a direc pah from power supply o ground does no exiss for any significan amoun of ime duraion. The shor circui power becomes a significan porion of oal power dissipaion when he CMOS inverer is loaded by larger RLC loads, creaing long ransiion imes. I is his condiion ha is of grea ineres when considering shor circui power in resisively loaded CMOS inverers. From able 3 and 4, we noe ha as he ime consan (RC or L/R) increases, shor-circui power dissipaion increases and becomes significan. The resisive power dissipaed for various RLC loads calculaed from (4) is shown in able 5 and 6. Table 5 represens he resisive power dissipaed by CMOS inverer driving RLC load for various R and C values for L=0.5nH. The average error is 8.49%. Noe ha as R is increased, he resisive power dissipaion also increases. Table 6 represens resisive power dissipaed by CMOS inverer driving RLC load for various R and L values for C=fF. The esimaed value is compared wih SPICE resul and average error is found o be as low as 4.76%. (a) (b) Figure 3. Oupu Response of a CMOS Inverer Driving a RLC Load TABLE I. PROPAGATION DELAY PD AND TRANSITION TIME r OF AN INERTER DRIING RLC LOAD FOR L=NH r (ps) PD (ps) R(Ω) L(nH) C(pF) Proposed Mehod SPICE % Error Proposed Mehod SPICE % Error nh k k For a given supply volage and frequency, dynamic power dissipaion depends only on load capaciance and does no depend upon he inpu waveform shape or load resisance. In conras, he shor circui power dissipaion 467

5 S. Sahoo e al, Journal of Elecron Devices, ol. 0, 0, pp changes wih inpu waveform shape as well as pu load resisance, inducance and capaciance. The raio of he oal ransien power (sum of dynamic power and shor-circui power) of a CMOS inverer wih respec o load resisance for differen inducance and capaciance are given in Figure 5 and 6, respecively. TABLE II. PROPAGATION DELAY PD AND TRANSITION TIME r OF AN INERTER DRIING RLC LOAD FOR C=PF r (ps) PD (ps) R(Ω) C(pF) L(nH) Proposed Mehod SPICE % Error Proposed Mehod SPICE % Error TABLE III k k pf k k k k k n.988n k 63.5n n 9.76 ESTIMATION OF SHORT-CIRCUIT POWER DISSIPATED BY A CMOS INERTER FOR L=0.5NH Power (mw), f=0.ghz, DD=.8 R(Ω) L(nH) C(pF) Proposed Mehod SPICE % Error k k k TABLE I. ESTIMATION OF SHORT-CIRCUIT POWER DISSIPATED BY A CMOS INERTER FOR C=FF Power (mw), f=0.ghz, DD=.8 R(Ω) L(nH) C(fF) Proposed Mehod SPICE % Error k k k k k k TABLE. RESISTIE POWER DISSIPATED BY A CMOS INERTER DRIING RLC LOAD FOR L=0.5NH Power(Wa),f=0.GHz, DD=.8 R(Ω) C(pF) Proposed Mehod SPICE % Error f 64.96f f f p p p.08p p.45p p 40.74p.75 0k f f 4.3 Figure 4. Shor-Circui Curren for a CMOS Inverer Driving Anoher Inverer TABLE I. RESISTIE POWER DISSIPATED BY A CMOS INERTER DRIING RLC LOAD FOR C=FF Power(Wa),f=0.GHz, DD=.8 R(Ω) L(nH) Proposed Mehod SPICE % Error f 44.47f f 9.649f 7.9 k 0.08p.037p k 0.84p.35p f 55.04f f 59.43f 6.85 k f 6.f 3. 0k f f f 0.599f p.643p 6.73 k p 3.544p k 80.68p 0.99p

6 S. Sahoo e al, Journal of Elecron Devices, ol. 0, 0, pp CONCLUSIONS A simple ye accurae expression for he pu volage of a CMOS inverer driving RLC load is presened in his paper. Wih his expression, equaions characerizing he propagaion delay and ransiion ime of a CMOS inverer driving RLC load are presened. This esimaed ransiion ime is compared wih SPICE resul for various R, L and C. For differen R, C and consan L he average error is 6.4% and for various R, L and consan C, he average error is.38%. Similarly he propagaion delays of CMOS inverer driving various RLC loads are esimaed and are compared wih SPICE. For various R, C and consan L, he average error is.58% and for various R, L and consan C, he average error is 3.7%. Since he pu waveform of his circui is accuraely modelled, he shor-circui power dissipaion of he following CMOS sage loading he inerconnec line is accuraely esimaed and compared wih SPICE. For differen R, C and consan L value, he average error is.7% and for differen R, L and consan C value, he average error is 0.%. The resisive power dissipaion is modelled and is compared wih SPICE value and for differen R, C and consan L value, he average error is 8.49% and for various R, L and consan C value, he average error is 4.76%. Therefore, due o he simpliciy and accuracy of hese expressions, he delay and power characerisics of a CMOS inverer driving high impedance RLC inerconnec line can be efficienly esimaed. Figure 5. Raio of Shor-Circui Power o Toal Power vs Load Resisance for Differen Capaciance alues and for L=0.5nH Figure 6. Raio of Shor-Circui Power o Toal Power vs Load Resisance for Differen Inducance alues and for C=fF References [] S.Bohra, B.Rogers, M.Kellam, and C.M. Osburn, Analysis of he effecs of scaling on inerconnec delay in ULSI circuis, IEEE Transacions on Elecron Devices ED-40, 59 (993). [] H. B. Bakoglu and J. D. Meindl, Opimal Inerconnecion Circuis for LSI, IEEE Transacions on Elecron Devices, ED-3,. 903 (985). [3] S. Dhar and M. A. Franklin, Opimum Buffer Circuis for Driving Long Uniform Lines IEEE Journal of Solid-Sae Circuis, SC-6, 3, (99). [4] M. Nekili and Y. Savaria, Opimal Mehods of Driving Inerconnecions in LSI Circuis, Proceedings of he IEEE Inernaional Symposium on Circuis and Syeems, pp. -3, May 99. [5] C. Y. Wu and M. Shiau, Delay Models and Speed Improvemen Techniques for RC Tree Inerconnecions among Small-Geomery CMOS Inserers, IEEE Journal of Solid-Sae Circuis, SC-5, 47, (990). [6] J. Cong and C. K. Koh, Simulaneous Driver and Wire Sizing for Performance and Power Opimizaion, IEEE Transacions on LSI Sysems LSI-, 408 (994). [7] R. J. Aninone and G. W. Brown, The modeling of Resisive Inerconnecs for Inegraed Circuis, IEEE Journal of Solid Sae Circuis SC-8, 00 (983). [8] L. Bisdounis, S. Nikolaidis, O. Koufopavlou, and C. E. Gis, Modeling he CMOS Shor-Circui Power Dissipaion, Proceedings of he IEEE Inernaional Symposium on Circuis and Sysems, pp , 4.47, May 996. [9] A. M. hill and S. M. Kang, Saisical Esimaion of Shor-Circui Power in LSI Circuis, IEEE Inernaional Symposium on Circuis and Sysems, pp , May 996. [0] A. Hiraa, H. Onodera, and K. Tamaru, Esimaion of shor-circui Power Dissipaion and is Influence on Propagaion Delay for Saic CMOS Gaes, IEEE Inernaional Symposium on Circuis and Sysems, pp , May 996. []. Adler and E. G. Friedman, Delay and Power Expressions of a CMOS inverer driving a Resisive-Capaciive Load, IEEE Inernaional Symposium on Circuis and Sysems, pp , May 996. [] A.I. Kayssi, K.A. Sakallah, and T. M. Burks, Analyical Transien Response of CMOS Inserers, IEEE ransacions on Circuis and Sysems-I CAS I-39, 4 (99). [3] N. Hedensierna and K. O. Jeppson, CMOS Circui Speed and Buffer Opimizaion, IEEE Transacions on CAD 6, 70 (987). [4] T. Sakurai and A. R. Newon, Alpha-Power Law MOSFET Model and is Applicaions o CMOS Inverer Delay and Oher Formulas, IEEE.Journal of Solid-Sae Circuis, SC 5,.584 (990). [5]. Adler and E. G. Friedman, Delay and Power Expressions of a CMOS inverer driving a Resisive-Capaciive Load, Analog Inegraed Circuis and Signal Processing, 4, 9 (997). [6] H. Shichman and D. A. Hodges, Modeling and Simulaion of Insulaed- Gae Field-Effec Transisor Swiching Circuis, IEEE Journal of Solid- Sae Circuis, SC-3, 85 (968). [7] H. J. M. eendrick, Shor-Circui Dissipaion of Saic CMOS Circuiry and Is Impac on he Design of Buffer Circuis; IEEE Journal of Solid- Sae Circuis, SC-9, 468 (984). [8] S. R. emuru and N. Scheinberg, Shor-Circui Power Dissipaion Esimaion for CMOS Logic Gaes, IEEE Transacions on Circuis and Sysems-I: Fundamenal Theory and Applicaions, CAS -4, 76 (994). [9] K.T. Tang, E.G. Friedman, "Delay and power expressions characerizing a CMOS inverer driving an RLC load," 000 IEEE Inernaional Symposium on Circuis and Sysems, ISCAS 000, Geneva, 3, pp [0] Susmia Sahoo, Madhumani Daa, and Rajib Kar Explici Delay and Power Esimaion Mehod for CMOS Inverer Driving On-Chip RLC Inerconnec Load, World Academy of Science, Engineering and Technology

7 S. Sahoo e al, Journal of Elecron Devices, ol. 0, 0, pp [] Madhumani Daa, Susmia Sahoo, Rajib Kar, An Explici Model for Delay and Rise Time for Disribued RC On-Chip LSI Inerconnec, IEEE Inernaional Conference on Signal and Image Processing(ICSIP), pp , Dec.5-7 h, 00, Chennai. [] Chandan Daa, Madhumani Daa, Sushmia Sahoo, Rajib Kar, A Closed Form Delay Esimaion Technique for High Speed On-Chip RLC Inerconnec Using Balanced Truncaion Mehod, IEEE Inernaional Conference on Devices and Communicaions (ICDeCom-), Feb 4-5, 0, pp. -4, BIT Mesra, India. [3] Rajib Kar,. Maheshwari, A. K. Mal, A. K. Bhaacharjee, Delay Analysis for On-Chip LSI Inerconnec using Gamma Disribuion Funcion, Inernaional Journal of Compuer Applicaion (Foundaion of Compuer Science (FCA) Press, USA),, 65 (00). [4] Rajib Kar, K. R. Reddy, A. K. Mal, A. K. Bhaacharjee, An Explici Approach for Dynamic Power Evaluaion for Deep submicron Global Inerconnecs wih Curren Mode Signalling Technique, Inernaional Journal of Recen Trends in Engineering (Academy Publisher, Finland), 3, 56 (00). [5] Rajib Kar, K. R. Reddy, A. K. Mal, A. K. Bhaacharjee, An Explici Approach for Dynamic Power Evaluaion for Deep submicron Global Inerconnecs wih Curren Mode Signalling Technique, Inernaional Journal of Recen Trends in Engineering (Academy Publisher, Finland), 3, 56 (00). 470