Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling *

Transcription

1 Calculaing Wors-Case Gae Delays Due o Dominan Capaciance Coupling * Florenin Daru Carnegie Mellon Universiy Deparmen of ECE, Pisburgh, PA 53 daru@ece.cmu.edu Lawrence T. Pileggi Carnegie Mellon Universiy Deparmen of ECE, Pisburgh, PA 53 pileggi@ece.cmu.edu ABSTRACT In his paper we develop a gae level model ha allows us o deermine he bes and wors case delay when here is dominan inerconnec coupling. Assuming ha he gae inpu windows of ransiion are known, he model can predic he wors and bes case noise, as well as he wors and bes case impac on delay. This is done in erms of a Ceff based gae model under general RC inerconnec loading condiions. I. INTRODUCTION As IC dimensions scale o he deep submicron range, heir muli-level inerconnecs are consruced such ha he coupling capaciance becomes he dominan componen of load capaciance. This effec is largely he resul of he increased raio beween he laeral and he verical capaciance of he line. The increased number of meal layers is he oher source of coupling capaciance problems, since here is a reduced likelihood of a nearby ground plan. The laeral capaciance is increased by he relaive increase in he meal hickness wih respec o line spacing ha is made o conrol resisance. T C V C L C L C V Figure : Cross-secion ino inerconnec sysem wih parasiic capaciances definiion. For example, Fig. shows a cross-secion of meal layers and he definiion for laeral (C L ) and verical (C V ) capaciances, meal hickness and widh. As in oher firs-order models [], we assume ha line spacing is equal o he line widh, and ha he meal hickness equals o he dielecric hickness. Using he parallel plae approximaion for he capaciances, we obain: C L T () C V W AR * This work was suppored in par by Inel Corporaion and he Semiconducor Research Corporaion under conrac DC-068. Permission o make digial/hard copy of all or par of his work for personal or classroom use is graned wihou fee provided ha copies are no made or disribued for profi or commercial advanage, he copyrigh noice, he ile of he publicaion and is dae appear, and noice is given ha copying is by permission of ACM, Inc. To copy oherwise, o republish, o pos on servers or o redisribue o liss, requires prior specific permission and /or a fee. DAC 97, Anaheim, California (c) 997 ACM /97/06..$3.50 W Meal lines where AR is he aspec raio (hickness/widh). Equaion () is inexac since fringing fields are no included. Considering he fringe effecs, his laeral vs. verical capaciance raio has a slighly weaker dependence on he aspec raio: C L AR n n [, ] () C V In [] i was repored ha he average meal aspec raio (defined as he sum of he aspec raio used for each layer divided by he number of meal layers) for Inel Corporaion processes (which is represenaive of he sae-of-he-ar) increases by.x per generaion. For 0.35µm echnology, he average aspec raio is.3, and in [] i is saed ha aspec raios of are sill desirable for RC delay benefis. From equaion () we observe ha he laeral capaciance, he main candidae for coupling beween lines, can be -4 imes bigger han he verical capaciance. This makes he effecive load capaciance of a line srongly dependen on he swiching aciviy of he signals o which i is coupled -- same direcion coupled-signal swiching speeds up he response, while opposie direcion swiching slows he response []. If he coupling capaciance dominaes he oal load capaciance, hen he line delay can vary by several hundreds of percen as a funcion of he swiching aciviy of nearby lines. Since inerconnec modeling and RC model order reducion have advanced significanly over he pas several years, i is no unfahomable o assume ha we can exrac he acual coupling capaciance and model coupling beween lines. Bu since we are suck in a paern of compuing gae delays only when linear grounded capaciors load he gae, we are immediaely faced wih he delicae problem of load modeling. Someimes he problem is approximaed by modeling he coupled capaciors as elemens o ground, wih modified values of capaciance. For example, for opposie direcion swiching of wo idenical, perfecly symmerical coupled lines, swiching a he same insan of ime, he coupling capaciance can be accuraely modeled as wice he amoun of capaciance o ground. While such an approximaion can someimes yield pessimisic delay approximaions, for he more realisic coupling cases (as we will show hrough an example) his doubling-he-coupling model does no predic an upper bound on he delay in general. To analyze noise due o capaciance coupling, one can sar wih a reduced order coupled inerconnec model and calculae he signals on a quie vicim line by superimposing he coupled signals from all oher lines. Such a model, while no exac, can render a reasonable approximaion since he nonlinear CMOS gae of he non-swiching vicim line is behaving like a ransisor in is linear region of operaion, and herefore, is modeled fairly well by a linear resisor. When we consider he impac of coupling on he delay, how-

2 ever, he vicim line is swiching, and he problem is much more complex. As he vicim line swiches, he impedance of is driving gae changes by orders of magniude, hereby influencing he amoun of coupling volage. Such effecs can be accuraely modeled in SPICE, bu due o he circui size, we would prefer o perform such analyses a he highes possible level of absracion. Empirical gae/cell level models remain popular for iming analysis, even for full cusom designs. In [3] a gae/cell level modeling mehodology was developed which achieves compaibiliy wih RC inerconnec loading hrough an effecive capaciance approximaion. In his paper we exend his waveform-based gae model o consider he problem of calculaing he delay (and response waveshape) when here is a significan amoun of coupling. The algorihms we develop in his paper for handling capaciive coupling permi wo approaches for obaining he bes/wors gae delay. Firs, we will ouline a mehodology for bounding he bes/wors gae delay. Second, due o he algorihm efficiency, a general opimizaion procedure is possible o generae accurae resuls. We will begin by firs reviewing some of he background of he C eff model in he following secion. Two cases of coupling of paricular ineres will be discussed in Secion III: single gae swiching and wo gaes wih capaciive loads simulaneously swiching. Our approach for he n capaciively coupled RC ree problem will be presened in Secion IV. Bounding he gae delay is he subjec of Secion V, followed by our conclusions in Secion VI. II. WAVEFORM-BASED GATE DELAY MODELS Gae delay modeling represens an aracive approach for iming analysis due o is simpliciy, speed and accuracy. For purely capaciive loads and sauraed ramp inpus, i is possible o characerize various oupu poins (e.g. 0%, 50%, 90%, ec.) as funcions of inpu ransiion ime, in, and oupu capaciance, C L : α f α ( in, C L ) (3) In (3), α is he percenage poin value, α is he oupu poin delay (w.r.. he 50% poin of he inpu signal) and f α is he corresponding delay descripion funcion. The delay descripion funcions can be obained in various ways. Boh analyical expressions obained using simplified MOS models [4,5] or empirical gae delay models [6] can be used o generae (3). Bu for he purpose of explanaion in his paper, we will assume empirical gae delay models. Empirical gae delay models are buil by running muliple SPICE simulaion wih he inpu ransiion ime and he oupu capaciance sweeping a specified range. The oupu poins of ineres are seleced from he SPICE resuls and hen an algebraic funcion (usually polynomial) or a look-up able is fied o he daa. The gae is ofen characerized in erms of oher parameers oo, such as emperaure, volage supply, variaions, ec. As he minimum feaure sizes for inegraed circuis scale downward, he inerconnec canno be modeled anymore by he linear grounded capacior assumed in he empirical gae models. The resisance of he inerconnec requires he use of RC driving poin and ransmiance models. Generally, hey are in he form of some reduced order models [7]. Bu even so, he simple RC loads are no single capaciors. In addiion, when he resisance is significan, he waveforms are no accuraely represened by jus rise/fall ime value [8]. Some aemps have been made o exend he empirical models o handle RC loads by increasing he number of parameers in he characerizaion. In [9] he RC load was modeled from he driving poin admiance poin of view as a π-circui, while he inpu signal was represened by hree parameers. This approach increases he number of SPICE runs required for characerizaion o very high levels (for example, from 6 o 4096 when considering every parameer sampled in 4 poins). I also has difficulies esablishing inpu parameer ranges and i is unable o give answers when he load requires higher order models han a C-R-C (π-model) circui. Anoher approache o achieve RC load compaibiliy employs he concep of effecive capaciance [,3]. Given any gae delay model (empirical or analyical) developed under purely capaciive load consrains, i maps he RC load ino a single capaciance value during an ieraive process o find he complee gae oupu waveform. Consider a Thevenin equivalen gae model as shown in Fig. a [3]. The model resisance, R d, is linear as described in [3]. I can be shown ha for any acual gae oupu waveform and R d value, an ideal Thevenin volage can be obained ha will allow he gae model oupu o perfecly mach he acual oupu. The Ceff ieraions are he process by which his volage is obained. in in IN IN n IN IN n V TH I N 0 f( in, C eff ) (a) 0 f( in, C eff ) g( in, C eff ) g( in, C eff ) (b) R d V TH () I N () Rircui Figure : Time-varying CMOS gae model as described in [3]: a) Thevenin equivalen; b) Noron equivalen. One way of hinking abou he Thevenin equivalen of a gae is o see i hrough he eyes of a simulaor. In a ransien analysis, a every ime poin he simulaor solves a nonlinear sysem, usually hrough a modified Newon-Raphson algorihm [0]. A every ieraion, he sandard Newon-Raphson algorihm linearizes every nonlinear elemen (represened by is I-V characerisic) as shown in Fig. 3a. A he las ieraion he rue operaing poin is obained and he corresponding linearizaion can be used o obain a Thevenin or Noron equivalen of he gae. The gae oupu resisance obained his way will have differen values a each ime poin and represens he acual small signal oupu resisance. The successive chord mehod [0] is anoher algorihm ha can be used o solve nonlinear sysems. Is linearizaion mehod is shown in Fig. 3b and implies a consan resisor value. The Thevenin or Noron gae equivalens will have he same oupu resisance for every ime poin. Because he successive chord mehod is as accurae as Newon-Raphson, is gae equivalens are also accurae. The successive chord mehod has a slower rae of nonlinear convergence in general, which is why N-R is more widely used for circui simulaion. The gae model presened in Fig. a is based on a linear approximaion of his ideal Thevenin volage waveform. The ramp-like shape of he Thevenin waveform was confirmed experi- R d v ou () v ou () Rircui

3 I i I j I j /R j I j R j i /R i I i R i V (a) (b) Figure 3: Linearizaion mehods for nonlinear ieraion algorihms: a) sandard Newon-Raphson and b) successive chord mehod. menally in []. I is ineresing o remark ha he errors of he ideal Thevenin waveform linearizaion are aenuaed a he model oupu due o he low-pass naure of he sysem. The Noron form of he Ceff model, shown in Fig. b, will be used in his paper. The I N seady sae values are 0 and V DD /R d. For a purely capaciive load, he model curren source (MCS) parameers, 0 and, are deermined by forcing he model oupu volage o be equal o he acual gae oupu volage for wo oupu poins (e.g. 0% and 50% poins): where v ou () is he model response for a capaciive load, ha depends on he model unknown parameers 0 and, C L is he load capaciance, in is he gae inpu ransiion ime and α ( in,c L ) is a gae delay model as in equaion (3). To achieve compaibiliy beween he RC load model and he gae equaions in (4), he effecive capaciance principle is applied: For every given gae, inpu ransiion ime and RC load, here exiss a C eff ha will force he same linearized Noron equivalen for he gae. In order o find his C eff value we force he equaliy of he average oupu volage for ( 0, 0 + ) for boh model driving C eff and he acual RC load: where v ou () is he model response for C eff load and v RC ou () is he model response for he acual load. I can be shown ha he average volage principle described in equaion (5) is mahemaically equivalen o he average curren principle described in [3]. This model is concepually exended in he following secions o model he coupling problem. III. GATE MODELS WITH DOMINANT COUPLING CAPACITANCE III. Single Gae Swiching We will firs consider he simples problem ha can be caused by coupling capaciance. The siuaion is described in Fig. 4a for wo inverers, bu exends o any oher ype of gae (buffers, NANDs, ec.). The wo drivers, one swiching and one quie, are loaded by inerconnec lines ha are capaciively coupled. The coupling capaciance is modeled by while C g and C g model I j I i I j /R c i I j R c /R c I i R c 0.V DD oupu rising v ou ( 0 ( in, C L )) 0.8V DD oupu falling v ou ( 50 ( in, C L )) V DD 0 + C ---- v eff ou C eff v RC ou 0 V (4) (5) he capaciance o ground. G G 0 C g g c π c π C G g g π d (a) (b) (c) Figure 4: Transforming he coupling capaciance problem wih one line quie ino an RC load problem: a) wo drivers, one swiching and one quie, wih heir loads coupled; b) he quie driver is replaced by is oupu resisance; c) he load of gae G is mapped ino a π-circui. The problem in Fig. 4 is a simplified one for wo reasons: Firs, due o he uncerainy of he inpu signal arrival imes, here is a non-zero probabiliy of overlapping ransiions for G and G. If we are cerain ha gae G will always swich while G is in seady sae, hen we don speak abou he bes/wors case delay for G (a leas from he coupling poin of view) bu raher he exac value. We have also negleced he inerconnec resisance, which we know is no possible in general. Bu we will remove hese simplificaions in laer secions. For his example we can safely replace gae G by a linear resisor o ground [3] as shown in Fig. 4b, whenever he noise ampliude a he oupu of G is small (up o 0-5% from V DD ) so ha he nonlinear variaions are negligeable. The error incurred in he noise ampliude due o his assumpion will be shown laer. The RC load in Fig. 4b can be exacly ranslaed ino a π-model load (Fig. 4c). The equivalen circui shown in Fig. 4c can be evaluaed by he effecive capaciance algorihm described in [3]. Firs of all, i should be noed ha he C eff value is bounded below and above by C π and (C π +C π C g + ), respecively. If dominaes C g and C g, hese bounds are no direcly useful. The Ceff gae model approximaion for he circui in Fig. 4c is shown in Fig G driving C π Inpu G driving C g + Ceff gae model driving he π-circui of Fig. 4c Acual oupu Time (ns) Figure 5: Driving poin waveforms for G from he circui shown in Fig. 4. Noe ha while his model is simplified, i sill capures he effec of he quie line gae resisance. A simple charge sharing model does no capure his effec. V noise V DD (6) + C g Where V noise is he ampliude of he coupling noise a he oupu of G generaed by a ransiion of G. For his example, equaion (6) will predic a noise ampliude of 6.5% from V DD, whereas he

4 simplified analysis in Fig. 5 is much more accurae. Once he Ceff model (Fig. ) for he example in Fig. 4 reaches convergence, he now linear circui represens a wo-pole sysem. The noise ampliude, herefore, can be compued analyically from he circui parameers (C g, C g, ) and he gae parameers (R d -- G oupu resisance, R d and of he G model as described in Fig. ). This compuaion is beyond he scope of his paper bu we will menion ha i accuraely predics he noise ampliude for our example: 5% from V DD. The single gae swiching case can be complicaed by aking ino consideraion he line resisance and he coupling o more han one oher line. These modificaions will only resul in a more complicaed driving poin admiance and ransfer funcion models, so he Ceff gae model approach sill applies. III. Two Swiching Gaes Coupled A much more ineresing, realisic, case is presened in Fig. 6a. Boh drivers can swich simulaneously and heir inpu signals are described as windows of arrival imes. For his siuaion we are ineresed in bes/wors cases a he oupus in order o generae he window of arrival imes for hose signals, and so on. G G C g C g G G (a) (b) (c) Figure 6: Two coupled gaes swiching simulaneously. a) general case; b) wors case scenario; c) Noron equivalen gae model applied o his problem. The imporan problem of how o find he pair of inpu gae signals ha will generae he bes/wors case for he oupu signals will be reaed laer. I is no difficul o observe ha he wors case scenarios can be differen for he wo gaes. Wihou loss in generaliy, we will sudy G s behavior under noise generaed by G. G will be referred o as he vicim, while G will be he aggressor. For he momen we will assume ha we know he wors case swiching condiions for he oupu of G, as shown in Fig. 6b. Wih he problem convered o a deerminisic one, we aemp o solve i wih he bes accuracy versus compuaion ime possible. We begin by viewing his circui from superposiion-like sandpoin. Of course our circui is highly nonlinear, so superposiion doesn acually apply, bu his view of he problem allows us o consider he aggressor as acing on he vicim. Saring wih his argumen we consider he following facs: he passive gae oupu resisance (R d in Fig. 4c) is nonlinear, spanning orders of magniude during a ransiion. I has a low value only if here is a pah of ransisors working in he linear region from he oupu o ground or V DD. The higher he resisance value a a given ime poin, he higher he noise ampliude will be. he noise injeced by G on R d depends on G s oupu waveform. Bu he rue oupu signal of G includes he noise injeced by G on G s oupu resisance. This convolued argumen is basically anoher way of saying ha superposiion doesn apply o nonlinear sysems. In solving his nonlinear, ime-dependen sysem, we have he opion o use he successive chord mehod for he nonlinear solver. Such a soluion scheme yields a Noron equivalen gae model wih consan oupu resisance upon convergence for all ime C g C g I N I N R d R d C g C g poins. The Noron curren source is a funcion of ime bu can be linearized wih reasonable accuracy so ha he Ceff gae responses can be approximaed. The Ceff model shown for he coupled sysem in Fig. 6c can be inerpreed as he resul of such a procedure. The ime varying gae model described in [3] successfully models single gaes swiching for a variey of loads. I compues he charge exchanged by he gae wih he load for a specific period during he ransiion and finds he effecive capaciance ha would ask for he same charge. Observing he currens hrough he coupling capaciance of Fig. 6 i is obvious ha here is no qualiaive difference beween hese currens and he curren delivered by a gae o a capaciive load. The noise curren is jus anoher load for he gae. Based on he above observaion we exended he effecive capaciance algorihm o he problem described in Fig. 6. Replacing he gaes by heir ime varying Noron equivalen, Fig. 6c, we form a sysem where he parameers of he curren sources, 0 s and s, are unknown. In order o incorporae he informaion from he empirical gae delay models we also inroduce an effecive capaciance for each gae. We mainain he same principles o solve for he unknowns: he charge delivered by he gae while is Noron curren source is in ransiion should be he same for he acual load (including noise curren) and for C eff load; he same Noron equivalen for he acual load and for C eff. he Noron equivalen parameers allow he model o fi wo poins of he acual gae response for capaciive load. The above principles ranslae in he following equaions:. 0 + acual acual Ceff where v Ceff () is he G model volage response for C eff load, v Ceff () is he G model volage response for C eff load, v acual () and v acual () are he G and G model volage responses, respecively, for he acual load (including noise conribuion). The model parameers, 0 s and s, are hidden inside hese model volage responses. The model responses o he acual loads can be wrien as: where I N (s) and I N (s) are he Laplace ransforms of he Noron equivalen curren sources and Z ij (s) are he z-parameers for he wo-por seen by he wo curren sources Ceff 0 0.V DD oupu rising 0.8V DD oupu falling v Ceff ( 0 ( in, C eff )) 0.V v DD oupu rising Ceff ( 0 ( in, C eff )) 0.8V DD oupu falling v Ceff ( 50 ( in, C eff )) V DD v Ceff ( 50 ( in, C eff )) V DD V acual ( s) I N ( s)z ( s) + I N ( s)z ( s) V acual ( s) I N ( s)z ( s) + I N ( s)z ( s) (7) (8)

5 The convergence properies for he Newon-Raphson procedure solving his 6x6 sysem are good. Only 5-7 ieraions are required o achieve.000 relaive accuracy. On a IBM PowerPC (Power Series he algorihm solves 300 bidimensional cases per second. Some resuls giving an idea abou he model accuracy are given in Fig Inpus Model oupu xcc grounded approximaion Acual driving poin waveforms 0 0 Time (ns) 0.75 Figure 7: Resuls for a circui like he one in Fig. 6a. I shows ha grounding wice he coupling capaciance does no provide an upper bound for he oupu signal. IV. CEFF APPROACH FOR CAPACITIVELY COUPLED RC INTERCONNECT The general problem we wan o solve is described in Fig. 8. Each of he n gaes drives an RC ree ha is capaciively coupled o oher RC rees (here is a dc pah from node x i o node y j,k if and only if ij). Wihou reducing he generaliy of he problem we arranged he drivers in he order of heir arrival ime. in s sn inn x x n Capaciive coupled RC Z L, Z Lm, Z L n, Z Lnmn, Figure 8: The problem saemen: n capaciive coupled RC rees wih heir drivers. Once we choose he Noron form for he gae model i is advisable o use a reduced order z-parameer represenaion for he N-por. We exend he effecive capaciance algorihm for his N- por problem by compuing a C eff value for each por, ogeher wih he gae model parameers, i.e. 0 and, for each driver (as in Secion III.). The unknowns are coupled ogeher, requiring he soluion of a (3N)x(3N) sysem. One hird of he sysem of equaions resuls from he averaging principle: he average volage a por i should equal he average volage delivered on he effecive capaciance of node i for a specified period of ime (in our case he ime period for which he i-h model curren source is in ransiion, i ). Therefore, 0i + i L I N s Z j ji s i 0i n j d 0i + i where Z ji (s) is he ransimpedance from node j o node i (Z ji (s)z ij (s) since he Rircuis are reciprocal). I should be noed ha he average volage principle is mahemaically equivalen o he curren averaging principle in [3]. y, y n,n vˆ ( C, effi ) d i 0i (9) The oher N equaions are obained by forcing he volage response of he C eff circui o saisfy he k-facor equaions for wo percenage poins: he 50% poin and anoher poin before i (we use he 0% poin) [3]. Accuracy resuls for a bidimensional coupling problem wih significan line resisance are given in Fig Model oupus Inpus No coupling approximaion for Acual driving poin waveforms Time (ns) Figure 9: Two drivers loaded by coupled RC lines. This example shows ha ignoring he coupling capaciance does no offer a secure lower bound. V. BEST/WORST GATE DELAY CASE In a iming analysis environmen, we only know min-max ranges for he inpu ransiion ime of each gae and he ime slack beween every pair of drivers. To find he se of hese variables ha generaes he bes/wors case for he oupu signals is a difficul problem. Tradiionally, his problem has been avoided by expressing he bes/wors case in erms of a modified coupling capaciance value. For example, o achieve he wors case, a grounded capacior equal o wice of he coupling capaciance is added o mimic he condiions of opposie direcion swiching. Bu as proved by he resuls in Fig. 7 and Fig. 9, his approach can give significan errors. From he oupu signal ransiion imes poin of view i is easy o observe ha he vicim should have he slowes oupu while he aggressors should be as fas as possible (for he bigges noise ampliude). This siuaion can be direcly ranslaed in erms of inpu ransiion ime. The condiions for he bes case are reversed. We will firs consider he formulaion of he problem which finds he wors case delay using linear driver models. Then we will exend he approach o he Ceff models. V. The Linear Case We are ineresed in he wors case delay for he sum of wo signals, named original signal and noise in Fig. 0. The only variable in his case is he ime shif beween he wo responses, s, defined from he beginning of he vicim signal o he peak of he noise. This is apparenly a difficul opimizaion problem where we have o worry abou local opima. Moreover, we have only an implici formula for he opimizaion goal, df. This will end o make is second derivaive w.r.. s overly complicaed..0 df Composie signal Original signal di Noise 0.0 V N 0 Time (ns) s Figure 0: Defining he variables involved in his problem.

6 However, here is a surprisingly simple soluion: he wors case delay for he composie signal corresponds o he ime, M in Fig., when he original signal crosses (-V N ). Therefore, we firs compue V N, which is a simpler opimizaion goal han calculaing df. For example, if his waveform is modeled as a wo-pole response (see Secion III.) we have an explici formula for he noise ampliude. I s undersood ha his noise is no so large ha i would exceed he noise margins..0 V N -V N V > V N M 0.00 Time (ns) Figure : The wors case delay for he problem presened in Fig. 0. Secondly, we solve for he ime when he original signal crosses (-V N ). These wo seps are significanly easier han a problem formulaion in erms of df direcly, since hey require wo roo finding soluions insead of a nonlinear opimizaion. Moreover, given ha here are pleny of inelligen iniial soluions, and ha an analyical roo finding soluion is available for a wo-pole sysem, he wo sep soluion approach is furher simplified. V. The Acual Problem Of course he acual problem is no linear. Thinking in erms of a Ceff model, boh he original signal and he noise waveforms are modified by heir relaive posiion which grealy complicaes finding he wors case. The observaion made on he linear problem can be used o upper bound he gae delay. The composie signal delay canno be bigger han wha resuls by using he maximum noise ampliude, max(v N ), and he slowes original signal. The maximum noise ampliude is obained by he fases aggressor. Because he vicim and he aggressor are on opposie ransiions, he vicim also slows down he aggressor. Consequenly, he quie vicim siuaion will lower bound he aggressor oupu ransiion ime and will upper bound he noise ampliude. Once we have deermined he maximum noise waveform, we pessimisically assume ha here is no influence of he vicim o he aggressor. For every ime shif of he aggressor Noron equivalen waveform, he vicim s Ceff is differen (because he average noise volage while he Noron curren source is in ransiion will be differen as shown by equaions (7) and (8)). As for purely capaciive loads, he gae response is slower for a bigger Ceff. An upper bound for he gae delay can be found by solving he problem described in Secion V., where he model response corresponding o maximum Ceff and he noise corresponding o he quie vicim are used. For more han one aggressor a similar procedure is applicable. Every aggressor is fases when all oher gaes are quie. The wors case noise waveforms will be summed such ha he resuling signal has he maximum ampliude. If he above bounds are no igh enough, a beer approximaion for he wors case delay can be generaed by anoher procedure based on he algorihm presened in Secion V.. In his case we model he effecs of shifing he noise on he original response by compuing he effecive capaciance corresponding o each ime shif. However, we ignore he effecs of he ime shif on he noise waveshape. Alhough he soluion given in Secion V. doesn upper bound he delay for his problem, i sill gives a good approximaion of he wors case. We sar by considering he bigges noise ampliude (for he quie vicim) and compue he vicim s maximum Ceff for his siuaion. This effecive capaciance is used o compue he new noise a he vicim s oupu and so on. For he examples shown in Fig. 7 and Fig. 9 his procedure converged wihin 5% of he wors/bes case in 3 ieraions. VI. CONCLUSIONS In his paper we discussed some of he problems generaed by he coupling capaciance. We have shown ha even for he simples case, single gae swiching and negligeable line resisance, he classical mehods of compuing noise ampliude and gae delay can generae large errors. In order o solve hese problems we exended a Noron equivalen gae model based on he effecive capaciance algorihm o handle he general problem of n drivers loaded by coupled RC loads. We presened muliple examples o prove he accuracy of wha we found o be a very fas algorihm. All of hese resuls are obained for a deerminisic se of inpu signals. In realiy, he bes we know abou he inpu signals arrival imes is heir window of uncerainy, an early and a lae arrival ime. Using he Ceff gae model i is possible o find bounds for he bes/wors case delay by viewing he coupled Ceff problem as analogous o he linear superposiion of wo waveforms. BIBLIOGRAPHY [] M. Bohr, Inerconnec scaling - he real limier o high performance ULSI, Inl. Elecronic Device Meeing, pp. 4-44, 995. [] H.B. Bakoglu, Circuis, inerconnecions, and packaging for VLSI, Addison-Wesley, 990. [3] F. Daru, N. Menezes, L.T. Pileggi, Performance compuaion for precharacerized CMOS gaes wih RC-loads, IEEE Transacions on CAD, vol. 5, pp , May 996. [4] T. Sakurai, A.R. Newon, Alpha-power model, and is applicaion o CMOS inverer delay and oher formulas, IEEE Journal of Solid Sae Circuis, vol. 5, pp , April 990. [5] A.I. Kayssi, K.A. Sakallah, T.M. Burks, Analyical ransien response of CMOS inverers, IEEE Transacions on CAS-I, vol. 39, pp 4-45, January 99. [6] N.H.E. Wese, K. Eshragian, Principles of CMOS VLSI Design, Addison-Wesley, 990. [7] L.T. Pillage, R.A. Rohrer Asympoic waveform evaluaion for iming analysis, IEEE Transacions on CAD, vol. 9, pp , 990. [8] F. Daru, L.T. Pileggi, Modeling signal waveshapes for empirical CMOS gae delay models, 6h Inl. Workshop PATMOS 96, pp , Bologna, Ialy, 996 [9] Y. Miki, M. Abe, Y. Ogawa, PCHECK: A delay ool for high performance LSI design, IEEE Cusom Inegraed Circuis Conference, pp , 995. [0] W.J McCalla, Fundamenals of compuer-aided circui simulaion, Kluwer Academic Publishers, 988. [] F. Daru, N. Menezes, J. Qian, L.T. Pillage A gae-delay model for high speed CMOS circuis, Proc. 3s ACM/IEEE Design Auomaion Conference, pp , 994. [] J. Qian, S. Pullela, L.T. Pillage, Modeling he effecive capaciance of he RC inerconnec, IEEE Transacions on CAD, vol. 3, pp , December 994. [3] P.R O Brian, T.L. Savarino, Modeling he driving-poin characerisic of resisive inerconnec for accurae delay esimaion, Proc. IEEE Inl. Conference Compuer-Aided Design, pp. 5-55, 989. [4] S.A. Kuhn, M.B. Kleiner, P. Ramm, W. Weber Inerconnec Capaciances, Crossalk, and Signal Delay in Verical Inegraed Circuis, Inl. Elecronic Device Meeing, pp. 49-5, 995.