EECS 141: FALL 00 MIDTERM 2
|
|
- Basil Whitehead
- 5 years ago
- Views:
Transcription
1 Universiy of California College of Engineering Deparmen of Elecrical Engineering and Compuer Science J. M. Rabaey TuTh9:30-11am EECS 141: FALL 00 MIDTERM 2 For all problems, you can assume he following ransisor parameers (unless oherwise menioned): NMOS: V Tn = 0.4, k n = 115 µa/v 2, V DSAT = 0.6V, λ = 0, γ = 0.4 V 1/2, 2Φ F = -0.6V PMOS: V Tp = -0.4V, k p = -30 µa/v 2, V DSAT = -1V, λ = 0, γ = -0.4 V 1/2, 2Φ F = 0.6V NAME Las Firs GRAD/UNDERGRAD Problem 1: Problem 2: Problem 3: Toal EECS 141: FALL 00 MIDTERM 2 1
2 PROBLEM 1: Inducance Consider he simple circui of FIG. 1, where he inverer is implemened using complimenary V ou CMOS. Assume ha he V in ransisors in he inverer GND can be modeled as consan linear resisors FIG. 1 Large Capaciance Driver (when on). = 2.5 V. C L = 25 pf.. a. Assuming a 1->0 ransiion a he inpu, deermine he ransisor resisances ha will resul in a 0 o 90% ransiion on he oupu of 5 nsec.. R NMOS = R PMOS = b. Draw he curren drawn from he supply as a funcion of ime during his low-o-high ransiion, and derive he appropriae equaions ha describe ha behavior. Assume ha he inpu signal has a very seep slope, and ha he ransisors swich insananeously. i VDD EECS 141: FALL 00 MIDTERM 2 2
3 c. The supply rails of he driver ( and GND) are conneced o an exernal off-chip supply wih a value of 2.5 V hrough bonding pads and wires wih a oal inducance of 7.5 nh. Draw he and GND signals as a funcion of ime for he ransiion described above, and annoae some meaningful values. You may assume ha he inroduced inducances do NOT impac he resuls of par b. GND d. Faced wih he emerging problem, rank-order he following remedies in order of poenial effeciveness. 1 being he mos effecive, 4 he leas - Inroduce a capaciance of 25 pf beween and GND. - Increase he 0-90% rise/fall imes a he oupu wih a facor of 2 by reducing he ransisor sizes. - Slow down he inpu signal o a fall ime of 1 nsec. - Use copper insead of aluminum for he supply disribuion nework. EECS 141: FALL 00 MIDTERM 2 3
4 Problem 2: Logic and Energy Jari Tukkola, a cellular phone designer a Nokia, has come up wih a bus-driving approach ha he believes is going o boh decrease energy consumpion and increase performance. To deliver he high performance, he has sared from a dynamic bus approach as shown in FIG. 2 for bi i. is se a 2.5 V. V bi In i C Li FIG. 2 Dynamic bus archiecure (bi i) a. Draw a iming diagram explaining he operaion of he circui (for he clock and inpu signals shown below). 0 V ini 0 V bi b. The swiching hreshold of he bus fanou inverers INV has been opimized for opimal performance. Explain wha Jari did o achieve his, and why. EECS 141: FALL 00 MIDTERM 2 4
5 c. For a bus widh of N=4, deermine he average energy dissipaed per clock cycle for he whole bus, assuming ha each inpu bi has a 50% chance of being a zero or a one. You may assume ha he capaciive load of he bus wire C Li = 10 pf dominaes all oher capaciances (including he clock capaciance, and he driver inverer). E ave = d. Jari believes ha he could reduce he average energy dissipaion of he bus if he would modify he circui along he lines of FIG. 3, which replaces he driving inverer by a NEXOR. The logic block F oupus a 1 if he number of 0 bis in he inpu word is larger han he number of 1 bis. For insance, F = 1, if In = 0010; F = 0, if In = 0011 or In = Explain why his idea of Jari migh no be a bad one afer all. V bi FIG. 3 Modified dynamic bus archiecure (bi i) F In i C Li In 0... In 3 EECS 141: FALL 00 MIDTERM 2 5
6 e. Design he gae ha implemens he logic block F. Derive firs he required logic funcion, and consequenly implemen he gae in saic complimenary CMOS. Make sure o size he ransisors appropriaely (his is, ake ino accoun he 3 imes lower driving capabiliy of he PMOS devices compared o NMOS, and assume ha he gae has o have a driving capabiliy equal o a minimum-sized NMOS inverer). F= e. Sill assuming ha each inpu bi has a 50% chance of being eiher a zero or a one, deermine again he average energy dissipaed per clock cycle. (WARNING - THIS MIGHT TAKE TIME TO FIGURE OUT. RESERVE THIS FOR DESSERT). E ave = EECS 141: FALL 00 MIDTERM 2 6
7 PROBLEM 3: Dynamic Logic Consider a convenional 4-sage Domino logic circui as shown in Figure 6 in which all precharge and evaluae devices are clocked using a common clock. For his enire problem, assume ha he pulldown nework is simply a single NMOS device (i.e., each Domino sage consiss of a dynamic inverer followed by a saic inverer). Assume ha each gae has a propagaion delay of T/2 (wih T a ime uni). Hence, he precharge ime of he dynamic gae is T/2, he evaluae ime of he dynamic gae is T/2 and he inverer lowo-high and high-o-low ransiions are each T/2. Assume ha he ransiions are ideal (zero rise/fall imes). IN Nework Ou 1 Nework Ou 2 Nework Ou 3 Nework Ou 4 Domino Sage FIG. 4 Convenional Domino Dynamic Logic. Assume he pulldown nework is a single NMOS device (i.e., each Domino sage consiss of a dynamic inverer followed by a saic inverer) (a) Complee he iming diagram for signals Ou 1, Ou 2, Ou 3 and Ou 4. IN Ou 1 Ou 2 Ou 3 Ou 4 T EECS 141: FALL 00 MIDTERM 2 7
8 Now consider he following variaion of he circui where he evaluae swich of he laer sages have been removed. IN Nework Ou 1 Nework Ou 2 Nework Ou 3 Nework Ou 4 Domino Gae FIG. 5 Convenional Domino Dynamic Logic wih he evaluae swiches removed in he laer sages. (b) Assume ha he clock is iniially in he precharge sae (=0 wih all nodes seled o he correc precharge saes), and he block eners he evaluae period (=1). Does he removal of he evaluae swiches help or hur he evaluaion. Explain. (c)assume ha he clock is iniially in he evaluae sae (=1), and he block eners he precharge sae ( = 0). Does he removal of he evaluae swiches help or hur he precharge. Explain. EECS 141: FALL 00 MIDTERM 2 8
Outline. Chapter 2: DC & Transient Response. Introduction to CMOS VLSI. DC Response. Transient Response Delay Estimation
Inroducion o CMOS VLSI Design Chaper : DC & Transien Response David Harris, 004 Updaed by Li Chen, 010 Ouline DC Response Logic Levels and Noise Margins Transien Response Delay Esimaion Slide 1 Aciviy
More informationPhysical Limitations of Logic Gates Week 10a
Physical Limiaions of Logic Gaes Week 10a In a compuer we ll have circuis of logic gaes o perform specific funcions Compuer Daapah: Boolean algebraic funcions using binary variables Symbolic represenaion
More informationEE 560 MOS INVERTERS: DYNAMIC CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS INVERTERS: DYNAMIC CHARACTERISTICS C gsp V DD C sbp C gd, C gs, C gb -> Oxide Caps C db, C sb -> Juncion Caps 2 S C in -> Ineconnec Cap G B D C dbp V in C gdp V ou C gdn D C dbn G B S C in
More informationEE141. EE141-Spring 2006 Digital Integrated Circuits. Administrative Stuff. Challenges in Digital Design. Last Lecture. This Class
-Spring 006 Digial Inegraed Circuis Lecure Design Merics Adminisraive Suff Labs and discussions sar in week Homework # is due nex hursday Everyone should have an EECS insrucional accoun hp://wwwins.eecs.berkeley.edu/~ins/newusers.hml
More informationChapter 4. Circuit Characterization and Performance Estimation
VLSI Design Chaper 4 Circui Characerizaion and Performance Esimaion Jin-Fu Li Chaper 4 Circui Characerizaion and Performance Esimaion Resisance & Capaciance Esimaion Swiching Characerisics Transisor Sizing
More informationEE 330 Lecture 40. Digital Circuits. Propagation Delay With Multiple Levels of Logic Overdrive
EE 330 Lecure 0 Digial ircuis Propagaion Delay Wih Muliple Levels of Logic Overdrive Review from Las Time Propagaion Delay in Saic MOS Family F Propagaion hrough k levels of logic + + + + HL HLn LH(n-1)
More informationEE 330 Lecture 41. Digital Circuits. Propagation Delay With Multiple Levels of Logic Overdrive
EE 330 Lecure 41 Digial ircuis Propagaion Delay Wih Muliple Levels of Logic Overdrive Review from Las Time The Reference Inverer Reference Inverer V DD R =R PD PU = IN= 4OX WMIN LMIN V IN M 2 M 1 L VTn.2VDD
More informationReading from Young & Freedman: For this topic, read sections 25.4 & 25.5, the introduction to chapter 26 and sections 26.1 to 26.2 & 26.4.
PHY1 Elecriciy Topic 7 (Lecures 1 & 11) Elecric Circuis n his opic, we will cover: 1) Elecromoive Force (EMF) ) Series and parallel resisor combinaions 3) Kirchhoff s rules for circuis 4) Time dependence
More informationDesigning Information Devices and Systems I Spring 2019 Lecture Notes Note 17
EES 16A Designing Informaion Devices and Sysems I Spring 019 Lecure Noes Noe 17 17.1 apaciive ouchscreen In he las noe, we saw ha a capacior consiss of wo pieces on conducive maerial separaed by a nonconducive
More informationMore Digital Logic. t p output. Low-to-high and high-to-low transitions could have different t p. V in (t)
EECS 4 Spring 23 Lecure 2 EECS 4 Spring 23 Lecure 2 More igial Logic Gae delay and signal propagaion Clocked circui elemens (flip-flop) Wriing a word o memory Simplifying digial circuis: Karnaugh maps
More informationCHAPTER 6: FIRST-ORDER CIRCUITS
EEE5: CI CUI T THEOY CHAPTE 6: FIST-ODE CICUITS 6. Inroducion This chaper considers L and C circuis. Applying he Kirshoff s law o C and L circuis produces differenial equaions. The differenial equaions
More informationHV513 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
H513 8-Channel Serial o Parallel Converer wih High olage Push-Pull s, POL, Hi-Z, and Shor Circui Deec Feaures HCMOS echnology Operaing oupu volage of 250 Low power level shifing from 5 o 250 Shif regiser
More informationdv 7. Voltage-current relationship can be obtained by integrating both sides of i = C :
EECE202 NETWORK ANALYSIS I Dr. Charles J. Kim Class Noe 22: Capaciors, Inducors, and Op Amp Circuis A. Capaciors. A capacior is a passive elemen designed o sored energy in is elecric field. 2. A capacior
More informationIntroduction to Digital Circuits
The NMOS nerer The NMOS Depleion oad 50 [ D ] µ A GS.0 + 40 30 0 0 Resisance characerisic of Q 3 4 5 6 GS 0.5 GS 0 GS 0.5 GS.0 GS.5 [ ] DS GS i 0 Q Q Depleion load Enhancemen drier Drain characerisic of
More informationSequential Logic. Digital Integrated Circuits A Design Perspective. Latch versus Register. Naming Conventions. Designing Sequential Logic Circuits
esigning Sequenial Logic Circuis Adaped from Chaper 7 of igial egraed Circuis A esign Perspecive Jan M. Rabaey e al. Copyrigh 23 Prenice Hall/Pearson Sequenial Logic pus Curren Sae COMBINATIONAL LOGIC
More information3. Alternating Current
3. Alernaing Curren TOPCS Definiion and nroducion AC Generaor Componens of AC Circuis Series LRC Circuis Power in AC Circuis Transformers & AC Transmission nroducion o AC The elecric power ou of a home
More informationINDEX. Transient analysis 1 Initial Conditions 1
INDEX Secion Page Transien analysis 1 Iniial Condiions 1 Please inform me of your opinion of he relaive emphasis of he review maerial by simply making commens on his page and sending i o me a: Frank Mera
More informationUniversity of Cyprus Biomedical Imaging and Applied Optics. Appendix. DC Circuits Capacitors and Inductors AC Circuits Operational Amplifiers
Universiy of Cyprus Biomedical Imaging and Applied Opics Appendix DC Circuis Capaciors and Inducors AC Circuis Operaional Amplifiers Circui Elemens An elecrical circui consiss of circui elemens such as
More informationHomework-8(1) P8.3-1, 3, 8, 10, 17, 21, 24, 28,29 P8.4-1, 2, 5
Homework-8() P8.3-, 3, 8, 0, 7, 2, 24, 28,29 P8.4-, 2, 5 Secion 8.3: The Response of a Firs Order Circui o a Consan Inpu P 8.3- The circui shown in Figure P 8.3- is a seady sae before he swich closes a
More informationChapter 7 Response of First-order RL and RC Circuits
Chaper 7 Response of Firs-order RL and RC Circuis 7.- The Naural Response of RL and RC Circuis 7.3 The Sep Response of RL and RC Circuis 7.4 A General Soluion for Sep and Naural Responses 7.5 Sequenial
More informationSilicon Controlled Rectifiers UNIT-1
Silicon Conrolled Recifiers UNIT-1 Silicon Conrolled Recifier A Silicon Conrolled Recifier (or Semiconducor Conrolled Recifier) is a four layer solid sae device ha conrols curren flow The name silicon
More informationChapter 6 MOSFET in the On-state
Chaper 6 MOSFET in he On-sae The MOSFET (MOS Field-Effec Transisor) is he building block of Gb memory chips, GHz microprocessors, analog, and RF circuis. Mach he following MOSFET characerisics wih heir
More informationEE 330 Lecture 41. Digital Circuits. Propagation Delay With Multiple Levels of Logic Optimally driving large capacitive loads
EE 330 Lecure Digial Circuis Propagaion Delay Wih uliple Levels of Logic Opimally driving large capaciive loads Review from Las Time Propagaion Delay in uliple- Levels of Logic wih Sage Loading nalysis
More informationDirect Current Circuits. February 19, 2014 Physics for Scientists & Engineers 2, Chapter 26 1
Direc Curren Circuis February 19, 2014 Physics for Scieniss & Engineers 2, Chaper 26 1 Ammeers and Volmeers! A device used o measure curren is called an ammeer! A device used o measure poenial difference
More informationInductor Energy Storage
School of Compuer Science and Elecrical Engineering 5/5/ nducor Energy Sorage Boh capaciors and inducors are energy sorage devices They do no dissipae energy like a resisor, bu sore and reurn i o he circui
More informationThe problem with linear regulators
he problem wih linear regulaors i in P in = i in V REF R a i ref i q i C v CE P o = i o i B ie P = v i o o in R 1 R 2 i o i f η = P o P in iref is small ( 0). iq (quiescen curren) is small (probably).
More informationEEEB113 CIRCUIT ANALYSIS I
9/14/29 1 EEEB113 CICUIT ANALYSIS I Chaper 7 Firs-Order Circuis Maerials from Fundamenals of Elecric Circuis 4e, Alexander Sadiku, McGraw-Hill Companies, Inc. 2 Firs-Order Circuis -Chaper 7 7.2 The Source-Free
More informationChapter 8 The Complete Response of RL and RC Circuits
Chaper 8 The Complee Response of RL and RC Circuis Seoul Naional Universiy Deparmen of Elecrical and Compuer Engineering Wha is Firs Order Circuis? Circuis ha conain only one inducor or only one capacior
More informationIntroduction to AC Power, RMS RMS. ECE 2210 AC Power p1. Use RMS in power calculations. AC Power P =? DC Power P =. V I = R =. I 2 R. V p.
ECE MS I DC Power P I = Inroducion o AC Power, MS I AC Power P =? A Solp //9, // // correced p4 '4 v( ) = p cos( ω ) v( ) p( ) Couldn' we define an "effecive" volage ha would allow us o use he same relaionships
More informationEECE251. Circuit Analysis I. Set 4: Capacitors, Inductors, and First-Order Linear Circuits
EEE25 ircui Analysis I Se 4: apaciors, Inducors, and Firs-Order inear ircuis Shahriar Mirabbasi Deparmen of Elecrical and ompuer Engineering Universiy of Briish olumbia shahriar@ece.ubc.ca Overview Passive
More informationNDS332P P-Channel Logic Level Enhancement Mode Field Effect Transistor
June 997 NS33P P-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion Feaures These P-Channel logic level enhancemen mode power field effec ransisors are produced using Fairchild's
More informationElectrical and current self-induction
Elecrical and curren self-inducion F. F. Mende hp://fmnauka.narod.ru/works.hml mende_fedor@mail.ru Absrac The aricle considers he self-inducance of reacive elemens. Elecrical self-inducion To he laws of
More informationModeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
Modeling he Overshooing Effec for CMOS Inverer in Nanomeer Technologies Zhangcai Huang, Hong Yu, Asushi Kurokawa and Yasuaki Inoue Graduae School of Informaion, Producion and Sysems, Waseda Universiy,
More information8. Basic RL and RC Circuits
8. Basic L and C Circuis This chaper deals wih he soluions of he responses of L and C circuis The analysis of C and L circuis leads o a linear differenial equaion This chaper covers he following opics
More informationPulse Generators. Any of the following calculations may be asked in the midterms/exam.
ulse Generaors ny of he following calculaions may be asked in he miderms/exam.. a) capacior of wha capaciance forms an RC circui of s ime consan wih a 0 MΩ resisor? b) Wha percenage of he iniial volage
More informationUT Austin, ECE Department VLSI Design 5. CMOS Gate Characteristics
La moule: CMOS Tranior heory Thi moule: DC epone Logic Level an Noie Margin Tranien epone Delay Eimaion Tranior ehavior 1) If he wih of a ranior increae, he curren will ) If he lengh of a ranior increae,
More informationLearning Objectives: Practice designing and simulating digital circuits including flip flops Experience state machine design procedure
Lab 4: Synchronous Sae Machine Design Summary: Design and implemen synchronous sae machine circuis and es hem wih simulaions in Cadence Viruoso. Learning Objecives: Pracice designing and simulaing digial
More information( ) = Q 0. ( ) R = R dq. ( t) = I t
ircuis onceps The addiion of a simple capacior o a circui of resisors allows wo relaed phenomena o occur The observaion ha he ime-dependence of a complex waveform is alered by he circui is referred o as
More informationChapter 4 AC Network Analysis
haper 4 A Nework Analysis Jaesung Jang apaciance Inducance and Inducion Time-Varying Signals Sinusoidal Signals Reference: David K. heng, Field and Wave Elecromagneics. Energy Sorage ircui Elemens Energy
More informationPhys1112: DC and RC circuits
Name: Group Members: Dae: TA s Name: Phys1112: DC and RC circuis Objecives: 1. To undersand curren and volage characerisics of a DC RC discharging circui. 2. To undersand he effec of he RC ime consan.
More informationELG 2135 ELECTRONICS I SIXTH CHAPTER: DIGITAL CIRCUITS
ELG 35 ELECTRONICS I SIXTH CHAPTER: DIGITAL CIRCUITS Session WINTER 003 Dr. M. YAGOUB Sixh Chaper: Digial Circuis VI - _ This las chaper is devoed o digial circuis and paricularly o MOS digial inegraed
More informationNDS356P P-Channel Logic Level Enhancement Mode Field Effect Transistor
March 996 NS356P P-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion These P-Channel logic level enhancemen mode power field effec ransisors are produced using Fairchild's proprieary,
More informationLabQuest 24. Capacitors
Capaciors LabQues 24 The charge q on a capacior s plae is proporional o he poenial difference V across he capacior. We express his wih q V = C where C is a proporionaliy consan known as he capaciance.
More informationQuad 2-Input OR Gate High-Performance Silicon-Gate CMOS
TECNICAL DATA Quad 2-Inpu OR ae igh-performance Silicon-ae CMOS The is idenical in pinou o he LS/ALS32. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih
More informationNDP4050L / NDB4050L N-Channel Logic Level Enhancement Mode Field Effect Transistor
April 996 NP45L / NB45L N-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion Feaures These logic level N-Channel enhancemen mode power field effec ransisors are produced using
More informationLecture -14: Chopper fed DC Drives
Lecure -14: Chopper fed DC Drives Chopper fed DC drives o A chopper is a saic device ha convers fixed DC inpu volage o a variable dc oupu volage direcly o A chopper is a high speed on/off semiconducor
More informationMC74HC138A. 1 of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demuliplexer High Performance Silicon Gae CMOS The is idenical in pinou o he LS8. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus.
More informationLab 10: RC, RL, and RLC Circuits
Lab 10: RC, RL, and RLC Circuis In his experimen, we will invesigae he behavior of circuis conaining combinaions of resisors, capaciors, and inducors. We will sudy he way volages and currens change in
More information- If one knows that a magnetic field has a symmetry, one may calculate the magnitude of B by use of Ampere s law: The integral of scalar product
11.1 APPCATON OF AMPEE S AW N SYMMETC MAGNETC FEDS - f one knows ha a magneic field has a symmery, one may calculae he magniude of by use of Ampere s law: The inegral of scalar produc Closed _ pah * d
More informationV L. DT s D T s t. Figure 1: Buck-boost converter: inductor current i(t) in the continuous conduction mode.
ECE 445 Analysis and Design of Power Elecronic Circuis Problem Se 7 Soluions Problem PS7.1 Erickson, Problem 5.1 Soluion (a) Firs, recall he operaion of he buck-boos converer in he coninuous conducion
More informationNDS355AN N-Channel Logic Level Enhancement Mode Field Effect Transistor
January 997 NS3AN N-Channel Logic Level Enhancemen Mode Field Effec Transisor General escripion Feaures SuperSOT TM -3 N-Channel logic level enhancemen mode power field effec ransisors are produced using
More informationL1, L2, N1 N2. + Vout. C out. Figure 2.1.1: Flyback converter
page 11 Flyback converer The Flyback converer belongs o he primary swiched converer family, which means here is isolaion beween in and oupu. Flyback converers are used in nearly all mains supplied elecronic
More information(b) (a) (d) (c) (e) Figure 10-N1. (f) Solution:
Example: The inpu o each of he circuis shown in Figure 10-N1 is he volage source volage. The oupu of each circui is he curren i( ). Deermine he oupu of each of he circuis. (a) (b) (c) (d) (e) Figure 10-N1
More informationCHAPTER 12 DIRECT CURRENT CIRCUITS
CHAPTER 12 DIRECT CURRENT CIUITS DIRECT CURRENT CIUITS 257 12.1 RESISTORS IN SERIES AND IN PARALLEL When wo resisors are conneced ogeher as shown in Figure 12.1 we said ha hey are conneced in series. As
More informationTopic Astable Circuits. Recall that an astable circuit has two unstable states;
Topic 2.2. Asable Circuis. Learning Objecives: A he end o his opic you will be able o; Recall ha an asable circui has wo unsable saes; Explain he operaion o a circui based on a Schmi inverer, and esimae
More informationi L = VT L (16.34) 918a i D v OUT i L v C V - S 1 FIGURE A switched power supply circuit with diode and a switch.
16.4.3 A SWITHED POWER SUPPY USINGA DIODE In his example, we will analyze he behavior of he diodebased swiched power supply circui shown in Figure 16.15. Noice ha his circui is similar o ha in Figure 12.41,
More informationEE100 Lab 3 Experiment Guide: RC Circuits
I. Inroducion EE100 Lab 3 Experimen Guide: A. apaciors A capacior is a passive elecronic componen ha sores energy in he form of an elecrosaic field. The uni of capaciance is he farad (coulomb/vol). Pracical
More information6.01: Introduction to EECS I Lecture 8 March 29, 2011
6.01: Inroducion o EES I Lecure 8 March 29, 2011 6.01: Inroducion o EES I Op-Amps Las Time: The ircui Absracion ircuis represen sysems as connecions of elemens hrough which currens (hrough variables) flow
More informationLinear Circuit Elements
1/25/2011 inear ircui Elemens.doc 1/6 inear ircui Elemens Mos microwave devices can be described or modeled in erms of he hree sandard circui elemens: 1. ESISTANE () 2. INDUTANE () 3. APAITANE () For he
More informationCLOSED FORM SOLUTION FOR DELAY AND POWER FOR A CMOS INVERTER DRIVING RLC INTERCONNECT UNDER STEP INPUT
Journal of Elecron Devices, ol. 0, 0, pp. 464-470 JED [ISSN: 68-347 ] CLOSED FORM SOLUTION FOR DELAY AND POWER FOR A CMOS INERTER DRIING RLC INTERCONNECT UNDER STEP INPUT Susmia Sahoo, Madhumani Daa, Rajib
More informationBasic Circuit Elements Professor J R Lucas November 2001
Basic Circui Elemens - J ucas An elecrical circui is an inerconnecion of circui elemens. These circui elemens can be caegorised ino wo ypes, namely acive and passive elemens. Some Definiions/explanaions
More informationRC, RL and RLC circuits
Name Dae Time o Complee h m Parner Course/ Secion / Grade RC, RL and RLC circuis Inroducion In his experimen we will invesigae he behavior of circuis conaining combinaions of resisors, capaciors, and inducors.
More informationChapter 10 INDUCTANCE Recommended Problems:
Chaper 0 NDUCTANCE Recommended Problems: 3,5,7,9,5,6,7,8,9,,,3,6,7,9,3,35,47,48,5,5,69, 7,7. Self nducance Consider he circui shown in he Figure. When he swich is closed, he curren, and so he magneic field,
More informationEECE 301 Signals & Systems Prof. Mark Fowler
EECE 3 Signals & Sysems Prof. Mark Fowler Noe Se # Wha are Coninuous-Time Signals??? /6 Coninuous-Time Signal Coninuous Time (C-T) Signal: A C-T signal is defined on he coninuum of ime values. Tha is:
More informationnon-linear oscillators
non-linear oscillaors The invering comparaor operaion can be summarized as When he inpu is low, he oupu is high. When he inpu is high, he oupu is low. R b V REF R a and are given by he expressions derived
More informationChapter 1 Electric Circuit Variables
Chaper 1 Elecric Circui Variables Exercises Exercise 1.2-1 Find he charge ha has enered an elemen by ime when i = 8 2 4 A, 0. Assume q() = 0 for < 0. 8 3 2 Answer: q () = 2 C 3 () 2 i = 8 4 A 2 8 3 2 8
More information1. Introduction. Rawid Banchuin
011 Inernaional Conerence on Inormaion and Elecronics Engineering IPCSIT vol.6 (011 (011 IACSIT Press, Singapore Process Induced Random Variaion Models o Nanoscale MOS Perormance: Eicien ool or he nanoscale
More informationUNIVERSITY OF CALIFORNIA AT BERKELEY
Homework #10 Soluions EECS 40, Fall 2006 Prof. Chang-Hasnain Due a 6 pm in 240 Cory on Wednesday, 04/18/07 oal Poins: 100 Pu (1) your name and (2) discussion secion number on your homework. You need o
More informationMC74HC165A. 8 Bit Serial or Parallel Input/ Serial Output Shift Register. High Performance Silicon Gate CMOS
MC74CA 8 Bi Serial or Parallel Inpu/ Serial Oupu Shif Regiser igh Performance Silicon Gae CMOS The MC74CA is idenical in pinou o he S. The device inpus are compaible wih sandard CMOS oupus; wih pullup
More informationElectrical Circuits. 1. Circuit Laws. Tools Used in Lab 13 Series Circuits Damped Vibrations: Energy Van der Pol Circuit
V() R L C 513 Elecrical Circuis Tools Used in Lab 13 Series Circuis Damped Vibraions: Energy Van der Pol Circui A series circui wih an inducor, resisor, and capacior can be represened by Lq + Rq + 1, a
More informationName: Total Points: Multiple choice questions [120 points]
Name: Toal Poins: (Las) (Firs) Muliple choice quesions [1 poins] Answer all of he following quesions. Read each quesion carefully. Fill he correc bubble on your scanron shee. Each correc answer is worh
More informationNDH834P P-Channel Enhancement Mode Field Effect Transistor
May 997 NH834P P-Channel Enhancemen Mode Field Effec Transisor General escripion Feaures SuperSOT TM -8 P-Channel enhancemen mode power field effec ransisors are produced using Fairchild's proprieary,
More informationEEC 118 Lecture #15: Interconnect. Rajeevan Amirtharajah University of California, Davis
EEC 118 Lecure #15: Inerconnec Rajeevan Amiraraja Universiy of California, Davis Ouline Review and Finis: Low Power Design Inerconnec Effecs: Rabaey C. 4 and C. 9 (Kang & Leblebici, 6.5-6.6) Amiraraja,
More information3.1.3 INTRODUCTION TO DYNAMIC OPTIMIZATION: DISCRETE TIME PROBLEMS. A. The Hamiltonian and First-Order Conditions in a Finite Time Horizon
3..3 INRODUCION O DYNAMIC OPIMIZAION: DISCREE IME PROBLEMS A. he Hamilonian and Firs-Order Condiions in a Finie ime Horizon Define a new funcion, he Hamilonian funcion, H. H he change in he oal value of
More informationBasic Principles of Sinusoidal Oscillators
Basic Principles of Sinusoidal Oscillaors Linear oscillaor Linear region of circui : linear oscillaion Nonlinear region of circui : ampliudes sabilizaion Barkhausen crierion X S Amplifier A X O X f Frequency-selecive
More informationChapter 2: Logical levels, timing and delay
28.1.216 haper 2: Logical levels, iming and delay Dr.-ng. Sefan Werner Winersemeser 216/17 Table of conen haper 1: Swiching lgebra haper 2: Logical Levels, Timing & Delays haper 3: Karnaugh-Veich-Maps
More informationAnalog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
TECHNICAL DATA IW0B Analog Muliplexer Demuliplexer HighPerformance SiliconGae CMOS The IW0B analog muliplexer/demuliplexer is digially conrolled analog swiches having low ON impedance and very low OFF
More informationU(t) (t) -U T 1. (t) (t)
Prof. Dr.-ng. F. Schuber Digial ircuis Exercise. () () A () - T T The highpass is driven by he square pulse (). alculae and skech A (). = µf, = KΩ, = 5 V, T = T = ms. Exercise. () () A () T T The highpass
More informationSOTiny TM LVDS High-Speed Differential Line Receiver. Features. Description. Applications. Pinout. Logic Diagram. Function Table
67890678906789067890678906789067890678906789067890678906789067890 SOTiny TM LVDS High-Speed Differenial Line Receiver Feaures Mees or Exceeds he Requiremens of NSI TI/EI-6-99 Sandard Signaling raes up
More informationES 250 Practice Final Exam
ES 50 Pracice Final Exam. Given ha v 8 V, a Deermine he values of v o : 0 Ω, v o. V 0 Firs, v o 8. V 0 + 0 Nex, 8 40 40 0 40 0 400 400 ib i 0 40 + 40 + 40 40 40 + + ( ) 480 + 5 + 40 + 8 400 400( 0) 000
More informationMath 333 Problem Set #2 Solution 14 February 2003
Mah 333 Problem Se #2 Soluion 14 February 2003 A1. Solve he iniial value problem dy dx = x2 + e 3x ; 2y 4 y(0) = 1. Soluion: This is separable; we wrie 2y 4 dy = x 2 + e x dx and inegrae o ge The iniial
More informationLecture 13 RC/RL Circuits, Time Dependent Op Amp Circuits
Lecure 13 RC/RL Circuis, Time Dependen Op Amp Circuis RL Circuis The seps involved in solving simple circuis conaining dc sources, resisances, and one energy-sorage elemen (inducance or capaciance) are:
More informationMC74HC595A. 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs. High Performance Silicon Gate CMOS
8-Bi Serial-Inpu/Serial or Parallel-Oupu Shif Regiser wih Lached 3-Sae Oupus High Performance Silicon Gae COS The C74HC55A consiss of an 8 bi shif regiser and an 8 bi D ype lach wih hree sae parallel oupus.
More information2.4 Cuk converter example
2.4 Cuk converer example C 1 Cuk converer, wih ideal swich i 1 i v 1 2 1 2 C 2 v 2 Cuk converer: pracical realizaion using MOSFET and diode C 1 i 1 i v 1 2 Q 1 D 1 C 2 v 2 28 Analysis sraegy This converer
More informationAC Circuits AC Circuit with only R AC circuit with only L AC circuit with only C AC circuit with LRC phasors Resonance Transformers
A ircuis A ircui wih only A circui wih only A circui wih only A circui wih phasors esonance Transformers Phys 435: hap 31, Pg 1 A ircuis New Topic Phys : hap. 6, Pg Physics Moivaion as ime we discovered
More informationSingle-Pass-Based Heuristic Algorithms for Group Flexible Flow-shop Scheduling Problems
Single-Pass-Based Heurisic Algorihms for Group Flexible Flow-shop Scheduling Problems PEI-YING HUANG, TZUNG-PEI HONG 2 and CHENG-YAN KAO, 3 Deparmen of Compuer Science and Informaion Engineering Naional
More informationV AK (t) I T (t) I TRM. V AK( full area) (t) t t 1 Axial turn-on. Switching losses for Phase Control and Bi- Directionally Controlled Thyristors
Applicaion Noe Swiching losses for Phase Conrol and Bi- Direcionally Conrolled Thyrisors V AK () I T () Causing W on I TRM V AK( full area) () 1 Axial urn-on Plasma spread 2 Swiching losses for Phase Conrol
More informationIntermediate Macro In-Class Problems
Inermediae Macro In-Class Problems Exploring Romer Model June 14, 016 Today we will explore he mechanisms of he simply Romer model by exploring how economies described by his model would reac o exogenous
More informationChapter 5-4 Operational amplifier Department of Mechanical Engineering
MEMS08 Chaper 5-4 Operaional amplifier Deparmen of Mechanical Engineering Insrumenaion amplifier Very high inpu impedance Large common mode rejecion raio (CMRR) Capabiliy o amplify low leel signals Consisen
More informationd i t e e dt units of time are s. Determine the total charge that has entered a circuit element for t 0. Answer:
Chaper Homework P.2-, 3, 4 P.3-2, 4 P.5-, 3, 5, 6, 7, 8 P.2. The oal charge ha has enered a circui elemen is q() =.25( e 5 ) when and q() = when
More informationOptimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product
010 3rd Inernaional Conference on VLSI Design Opimized Sage Raio of Tapered CMOS Inverers for Minimum Power and Mismach Jier Produc R. Dua*, T. K Bhaacharyya*, X. Gao and E. A. M. Klumperink *E & ECE Deparmen,
More informationdv i= C. dt 1. Assuming the passive sign convention, (a) i = 0 (dc) (b) (220)( 9)(16.2) t t Engineering Circuit Analysis 8 th Edition
. Assuming he passive sign convenion, dv i= C. d (a) i = (dc) 9 9 (b) (22)( 9)(6.2) i= e = 32.8e A 9 3 (c) i (22 = )(8 )(.) sin. = 7.6sin. pa 9 (d) i= (22 )(9)(.8) cos.8 = 58.4 cos.8 na 2. (a) C = 3 pf,
More informationLecture 15: Differential Pairs (Part 2)
Lecure 5: ifferenial Pairs (Par ) Gu-Yeon Wei ivision of Enineerin and Applied Sciences Harvard Universiy uyeon@eecs.harvard.edu Wei Overview eadin S&S: Chaper 6.6 Suppleenal eadin S&S: Chaper 6.9 azavi,
More informationSmart Highside Power Switch PROFET
Smar ighside Power Swich PROFET BTS 410E2 Feaures TO220AB/ Overload proecion Curren limiaion Shor circui proecion Thermal shudown 1 1 Overvolage proecion (including Sandard Sraigh leads SMD load dump)
More informationChapter 15: Phenomena. Chapter 15 Chemical Kinetics. Reaction Rates. Reaction Rates R P. Reaction Rates. Rate Laws
Chaper 5: Phenomena Phenomena: The reacion (aq) + B(aq) C(aq) was sudied a wo differen emperaures (98 K and 35 K). For each emperaure he reacion was sared by puing differen concenraions of he 3 species
More informationThe general Solow model
The general Solow model Back o a closed economy In he basic Solow model: no growh in GDP per worker in seady sae This conradics he empirics for he Wesern world (sylized fac #5) In he general Solow model:
More informationModule 2 F c i k c s la l w a s o s f dif di fusi s o i n
Module Fick s laws of diffusion Fick s laws of diffusion and hin film soluion Adolf Fick (1855) proposed: d J α d d d J (mole/m s) flu (m /s) diffusion coefficien and (mole/m 3 ) concenraion of ions, aoms
More informationR.#W.#Erickson# Department#of#Electrical,#Computer,#and#Energy#Engineering# University#of#Colorado,#Boulder#
.#W.#Erickson# Deparmen#of#Elecrical,#Compuer,#and#Energy#Engineering# Universiy#of#Colorado,#Boulder# Chaper 2 Principles of Seady-Sae Converer Analysis 2.1. Inroducion 2.2. Inducor vol-second balance,
More informationMechanical Fatigue and Load-Induced Aging of Loudspeaker Suspension. Wolfgang Klippel,
Mechanical Faigue and Load-Induced Aging of Loudspeaker Suspension Wolfgang Klippel, Insiue of Acousics and Speech Communicaion Dresden Universiy of Technology presened a he ALMA Symposium 2012, Las Vegas
More information10. State Space Methods
. Sae Space Mehods. Inroducion Sae space modelling was briefly inroduced in chaper. Here more coverage is provided of sae space mehods before some of heir uses in conrol sysem design are covered in he
More information