Physical Limitations of Logic Gates Week 10a

Transcription

1 Physical Limiaions of Logic Gaes Week 10a In a compuer we ll have circuis of logic gaes o perform specific funcions Compuer Daapah: Boolean algebraic funcions using binary variables Symbolic represenaion of funcions using logic gaes Example: A B Every node has capaciance and inerconnecs have resisance. I akes ime o charge hese capaciances. Thus, oupu of all circuis, including logic gaes is delayed from inpu. For example we will define he uni gae delay C D

2 UNIT GATE DELAY τ D Time delay τ D occurs beween inpu and oupu: compuaion is no insananeous Value of inpu a = 0 deermines value of oupu a laer ime = τ D Logic Sae A B C 1 Inpu (A and B ied ogeher) Oupu 0 0 τ D

3 UNIT GATE DELAY τ D in ASYNCHRONOUS LOGIC Time delay τ D is measured from he las inpu change Logic Sae A B C Inpu A Inpu B Oupu 0 0 τ D

4 Synchronous and Asynchronous Logic Time delay occurs beween inpu and oupu in real logic circuis. Therefore he ime a which oupu appears is difficul o predic i depends for example on how many gaes you go hrough. A B CK C We will ofen no disinguish asynchronous vs synchronous logic. To make logic operaions as fas as possible, we need predicabiliy of signal availabiliy. Tha is we wan o know exacly when C is correcly compued from A and B. This requiremen argues for synchronous logic, in which a clock signal CK acually iniiaes he compuaion of C. Thus in he modified gae, C will be valid precisely one gae delay (τ D ) afer he clock inpu CK, goes high (A and B are evaluaed precisely when CK goes high, wha hey do before or afer his is irrelevan; CK mus go low, hen high again before he NAND gae again looks a A and B).

5 EFFECT OF GATE DELAY Cascade of Logic Gaes A B D C Inpus have differen delays, bu we ascribe a single worscase delay τ D o every gae How many gae delays for shores pah? ANSWER : How many gae delays for longes pah? ANSWER : 3 Which pah is he imporan one? ANSWER : LONGEST

6 TIMING DIAGRAMS Show ransiions of variables vs ime A B Logic sae D A,B,C C Noe B becomes valid one gae delay afer B swiches ( B C) Noe ha becomes valid wo gae delays afer B&C swich, because he inver funcion akes one delay and he NAND funcion a second. No change a = 3 τ D ( B C) ( A D 0 B) τ D τ D B τ D τ D τ D τ D 3τ D

7 WHAT IS THE ORIGIN OF GATE DELAY? Logic gaes are elecronic circuis ha process elecrical signals Mos common signal for logic variable: volage Specific volage ranges correspond o 0 or 1 Vol s Thus delay in volage rise or fall (because of delay in charging 3 inernal capaciances) will ranslae Range 1 o a delay in signal iming 1 0 Gray area... no allowed Range 0 Noe ha he specific volage range for 0 or 1 depends on logic family, and in general decreases wih logic generaions

8 VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverer inpu is v IN (), oupu is v OUT () v IN () v OUT () V in () inside a large sysem

9 GATE DELAY (PROPAGATION DELAY) Define τ as he delay required for he oupu volage o reach 50% of is final value. In his example we will use 3V logic, so halfway poin is 1.5V. Inverers are designed so ha he gae delay is symmerical (rise and fall) V in () 1.5 V ou () Approximaion 1.5 τ D τ D τ D

10 EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Compuer archiecs would like each sysem clock cycle o have beween 0 and 50 gae delays use 35 for calculaions Implicaion: if clock frequency = 500 MHz clock period = ( s 1 ) 1 Period = 10 9 s = ns (nanoseconds) Gae delay mus be τ D = (1/35) Period = ( ns)/35 = 57 ps (picoseconds) How fas is his? Speed of ligh: c = m/s Disance raveled in 57 ps is: C X τ D = (3x10 8 m/s)(57x10 1s ) = 17 x 10 4 m = 1.7cm

11 WHAT DETERMINES GATE DELAY? v IN () v OUT () The delay is mosly simply he charging of he capaciors a inernal nodes. We already know how o analyze his.

12 Example The gae delay is simply he charging of he capaciors a inernal nodes. Oversimplified example using ideal inverer, II v OUT () and 5V logic swing v IN () v OUT () 5 Vx R MODEL v IN () II v OUT () RC = C 0.1ns 5 v IN.5.5 Vx v OUT v IN () RC = 0.1ns so 0.069ns afer v IN swiches by 5V, Vx moves.5v τ D = 0.069ns

13 Simple model for logic delays Model acual logic gae as an ideal logic gae fed by an RC nework which represens he dominan R and C in he gae. v IN () R C Ideal v OUT () V X Logic gae Ideal Logic gae ec. Acual Logic Gae v OUT () v IN () v IN v OUT V X τ D = RC

14 How can we build inverers, NAND gaes, ec.? We need some sor of conrolled swich: ha is a device in which a swich opens or closes in response o an inpu volage (a conrol volage). If we have a conrolled swich i is an easy maer o build inverers, NAND gaes, ec. For example an elecromagneic relay has a coil producing a magneic field causing some conacs o snap shu when a volage is applied o he coil. Les imagine a simple conrolled swich, bu include in i some resisance (all real devices have nonzero resisance).

15 Conrolled Swich Model I Oupu I vs. V Inpu R I Oupu Inpu low Inpu high V The basic idea: We need a swich which is conrolled by an inpu volage. For example: Inpu V = 0 means he swich is open, whereas an inpu volage of V means ha he swich is closed (We will call his a Type N conrolled swich )

16 Conrolled Swich Model Inpu Inpu G G S S R N R P Oupu Oupu Type N conrolled swich means swich is closed if inpu is high. (V G > V S ) Type P conrolled swich means swich is closed if inpu is low. (V G < V S ) Now les combine hese swiches o make an inverer.

17 Conrolled Swich Model of Inverer V IN Inpu V DD = V V SS = 0V S P R P R N S N S P is closed if V IN < V DD S N is closed if V IN > V SS Oupu V OUT So if V IN is V hen S N is closed and S P is open. Hence V OUT is zero. Bu if V IN is 0V hen S P is closed and S N is open. Hence V OUT is V.

18 Conrolled Swich Model of Inverer V DD = V V IN =V V SS = 0V V OUT R N IF V IN is V hen S N is closed and S P is open. Hence V OUT is zero (bu driven hrough resisance R N ). V DD = V V IN =0V R P V SS = 0V V OUT Bu if V IN is 0V hen S P is closed and S N is open. Hence V OUT is V (bu driven hrough resisance R P ).

19 Conrolled Swich Model of Inverer V DD = V V IN =V V SS = 0V V OUT R N IF here is a capaciance a he oupu node (here always is) hen V OUT responds o a change in V IN wih our usual exponenial form. V DD = V V OUT V IN jumps from V o 0V V IN =0V R P V SS = 0V V OUT V IN jumps from 0V o V

20 Conrolled Swich Model of Inverer We will expand on his model in coming weeks. The conrolled swiches will of course be MOS ransisors. The resisance will be he effecive oupu resisance of he MOS devices. The capaciance will be he inpu capaciance of he MOS devices. Bu now les briefly review he energy used in charging and discharging capaciances so we can sar o esimae chip power.

21 ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS A REVIEW CASE 1 Charging V DD i R C =0 R D Capacior iniially uncharged (Q=CV DD a end) Swich =0 Power ou of "baery" P = i()v DD Energy ou of "baery" E = ivddd 0 = QVDD = CV DD Power ino C P C = i()v C () Energy ino C E C = ivc d 0 1 = CV DD Power ino R PR = [ i() ] R Energy ino R (hea) This mus be difference of E and E C, i.e. 1 CV DD

22 ENERGY AND POWER IN CHARGING V DD R C =0 R D Capacior iniially uncharged (Q=CV DD a end) Swich =0 Energy ou of "baery" = CV DD Energy ino C 1 = CV DD Energy ino R (hea) 1 CV DD In charging a capacior from a fixed volage source V DD half he energy from he source is delivered o he capacior, and half is los o he charging resisance, independen of he value of R.

23 ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS CASE discharging V DD R i C =0 R D Capacior iniially charged (Q=CV DD ) and discharges. Swich =0 Power ou of baery =0 Energy ou of baery =0 Power in/ou of R =0 Power ou of C P C = i()v C () Energy ou of C E C = ivc d 0 1 = CV DD Power ino R D P [ i() ] R = R Energy ino R D (hea) This mus be energy iniially in C, i.e. 1 CV DD

24 ENERGY IN DISCHARGING CAPACITORS V DD R C =0 R D Capacior iniially charged (Q=CV DD ) and discharges. Swich =0 Energy ou of C 1 = CV DD Energy ino R D (hea) 1 CV DD When a capacior is discharged ino a resisor he energy originally sored in he capacior (1/ CV DD ) is dissipaed as hea in he resisor

25 POWER DISSIPATION in DIGITAL CIRCUITS Each node ransiion (i.e. charging or discharging) resuls in a loss of (1/)(C)(V DD ) How many ransiions occur per second? Well if he node is pulsed up hen down a a frequency f (like a clock frequency) hen we have f dissipaion evens. A sysem of N nodes being pulsed a a frequency f o a signal volage V DD will dissipae energy equal o (N) (f )(½CV DD ) each second Therefore he average power dissipaion is (N) (f )(CV DD )

26 LOGIC POWER DISSIPATION Power = (Number of gaes) x (Energy per cycle) x (frequency) N = 10 7 ; V DD = V; node capaciance = 10 ff; f = 10 9 s 1 (1GHz) P = 400 W! a oaser! P = (N) (CV DD ) (f ) Prey high bu realisic Wha o do? (N increases, f increases, hmm) 1) Lower V DD ) Turn off he clock o he inacive nodes Clever archiecure and design! Les define α as he fracion of nodes ha are clocked (acive). Then we have a new formula for power.

27 LOGIC POWER DISSIPATION wih power miigaion Power = (Energy per ransiion) x (Number of gaes) x (frequency) x fracion of gaes ha are acive (α). P = α N f CV DD In he las 5 years V DD has been lowered from 5V o abou 1.5V. I canno go very much lower. Bu wih clever design, we can make α as low as 1 or 10%. Tha is we do no clock hose pars of he chip where here is no compuaion being made a he momen. Thus he 400W example becomes 4 o 40W, a manageable range (4W wih hea sink, 40W wih hea sink plus fan on he chip).