Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
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1 Modeling he Overshooing Effec for CMOS Inverer in Nanomeer Technologies Zhangcai Huang, Hong Yu, Asushi Kurokawa and Yasuaki Inoue Graduae School of Informaion, Producion and Sysems, Waseda Universiy, Kiakyushu, Japan Sanyo Semiconducor Co., Ld, Gunma, Japan 1
2 Ouline Background Analyical expressions for overshooing effec Considering process variaion Simulaion resuls Conclusions 2
3 Ouline Background Analyical expressions for overshooing effec Considering process variaion Simulaion resuls Conclusions 3
4 The differenial equaion for he CMOS inverer PMOS Ip Vin I CM CM I CL Vou The inpu volage for he falling inpu ramp is expressed as NMOS In C M is known as he Miller effec, bu is seldom of imporance in digial circuis. I is, however, of major imporance in analog circuis. Principles of CMOS VLSI Design: A Sysems Perspecive
5 I. Background 1 2 D = 50 in D = ov + r 1 2 in For radiional process echnologies, he effec of overshooing is very small and can be negleced 5
6 I. Background The influence of overshooing ime on iming analysis r and d decrease much faser han ov wih he increasing of gae sizes. And ov is equal o or larger han r. Wih he scaling of echnology process, ov becomes much imporan for delay ime. 6
7 I. Background The influence of overshooing ime on power analysis Shor-circui power consumpion The overshooing ime is one imporan parameer for power consumpion esimaion. 7
8 I. Background Convenional models for overshooing ime The overshooing ime is negleced ov =0. The overshooing ime is assumed as simple value ov = (V /V dd ) in empirical expressions J. L. Rossell, Charge-based analyical model for he evaluaion of power consumpion, TCAD
9 Ouline Background Analyical expressions for overshooing effec Considering process variaion Simulaion resuls Conclusions 9
10 300 PMOS Ip Charging period I CM CM I CL Curren (ua) Discharging period Q 2 I L ( ov ) NMOS In 50 Q 1 vmin Times (ps) ov
11 II. Proposed Model PMOS Ip Vin I CM I CM I CL Vou NMOS In I n C L I CL dvin C M Vou () = d 1 e β ( ˆ n VGS VTHN ) β ( Vˆ V ) n GS THN C L + C M
12 II. Proposed Model Charging period 400 Curren (ua) Discharging period I L ( ov ) Curren (ua) I p I n 0 Q p ov 50 Q 1 vmin Times (ps) ov 0 vmin Times (ps) 12
13 II. Proposed Model Minimum overshooing ime The overshooing ime has minimum values. D = ov + r 1 2 in Minimum delay > Minimum overshooing ime 13
14 Ouline Background Analyical expressions for overshooing effec Considering process variaion Simulaion resuls Conclusions 14
15 III. Considering Process Variaion In recen echnologies, he variabiliy of circui performance due o he process variaion has become a significan concern. As process geomeries coninue o shrink, he evaluaion for criical device parameers is becoming more and more difficul due o he significan variaions The sensiiviies of he overshooing ime wih respec o he variaion sources. Wih respec o he variaion of lengh. Wih respec o he variaion of hreshold volage. 15
16 III. Considering Process Variaion D = ov + r 1 2 in Variaion of L has no influence on he overshooing ime. Variaion of L has he influence only on he rising ime. Variaion of L has significan influence on he gae delay. D. Sinha, Gae Sizing Using Incremenal Parameerized Saisical Timing Analysis ICCAD
17 III. Considering Process Variaion 1. Wih inpu ime decreases, he influence due o he Tox decreases grealy. 2. The influence due o L is Wih he scaling of process echnologies, he variaion of V increases, he influence due o V will increase grealy. Inernaional Technology Roadmap for Semiconducors (ITRS)
18 Ouline Background Analyical expressions for overshooing effec Considering process variaion Simulaion resuls Conclusions 18
19 IV. Simulaion Resuls J.L. Rossell: Charge-based analyical model for he evaluaion of power consumpion in submicron CMOS buffers, TCAD
20 IV. Simulaion Resuls J.L. Rossell: Charge-based analyical model for he evaluaion of power consumpion in submicron CMOS buffers, TCAD
21 Ouline Background Analyical expressions for overshooing effec Considering process variaion Simulaion resuls Conclusions 21
22 V. Conclusions The inpu-o o-oupu oupu coupling capaciance has been proved o has significan influence on CMOS gaes: iming analysis and power analysis. The overshooing ime has become one of main pars of gae delay. The analyical model for overshooing ime is derived. 1. The overshooing ime has minimum value 2. Gae delay canno be smaller han his minimum value. Considering process variaion: 1. The variaion due o L has he influence only on oupu rising ime, bu has almos no influence on overshooing ime. 2. The variaion due o V has he mos significan influence on overshooing ime wih he scaling of echnologies. 22
23 Thank you for your aenions 23
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