CHAP.4 Circuit Characteristics and Performance Estimation

Transcription

1 HAP.4 ircui haracerisics and Performance Esimaion 4. Resisance esimaion R ρ l w (ohms) where ρ Resisiviy Thickness l onducor lengh w onducor widh l R Rs w where Rs Shee resisance (Ω/square) in 0.5µm o 1.0µm MOS processes 00/4/18 1

2 * hannel resisance R c k W 1 gs 1 ( ) W µ ox gs 1 k, k 1,000~30,000Ω/square µ ( ) ox 1 gs Typical shee resisance for conducors (Table 4.1) hannel resisance + 0.5% per Meal and poly % per Well diffusion % per Resisance for nonrecangular regions (Fig 4.) 4.3 apaciance esimaion Running/Swiching speed of MOS Parasiic MOS capaciance + Runners (wired poly, meal, diffusion) x (device and conducor resisance) Toal loading capaciance 1. Gae capaciance (of oher inpu). Diffusion capaciance (of he drain regions) 3. Rouing capaciance (of connecions beween O/P & I/P) To esimae he speed of he device ( R and informaion) MOS-apacior haracerisics (**wihou Source and Drain) Accumulaion g < 0 Gae volage Depleion g 0 Inversion g > 0 00/4/18

3 (a) Accumulaion layer is direcly conneced o subsrae. Gae capaciance can be approximaed by o ε ε SiO 0 ox A (4.4) where A Area of gae Relaive permiiviy Of SiO 3.9 ЄSiO Dielecric consan Є0 Permiiviy of free space (b) Depleion mode : Funcion of : (1) Doping concenraion (N) () Elecronic charge (q) (3) Depleion deph (d) (c) Inversion 00/4/18 gb o in series wih dep, where gb(gae-o-bulk(subs)) 0 dep gb + (varied as a funcion of gs) dep ε 0 ( 1) dep 0 + εsi d dep dep A min ε Si, low frequency, high frequency ( < 100 Hz ) 3

4 MOS Device capaciance ircui symbol gs, gd Gae-o-channel capaciance (Inpu par) sb, db Source/drain diff-o-bulk (subs) capaciance (Oupu par) gb Gae-o-bulk capaciance (Inpu) Toal gae capaciance g of an MOS device (or so-called inpu capaciance) g gb + gs + gd (a) Off-region : ( gs < ) No channel gs gd 0 g gb o + dep (b) Non-sauraion region : ( gs - > ds ) gd gs ε0ε ox 0 gb 1 SiO A (c) Sauraed region : ( gs - < ds ) hannel is heavily invered pinch off gd 0 gs ε 0 ε SiO 3 ox A Approximaion of MOS gae capaciance 00/4/18 4

5 onservaive approximaion: g o ox A where ox : hin-oxide capaciance per uni area. ε0ε SiO 35 µ m ox ο ο 4 ( 17) 10 pf 100Α ~ 00Α ox () (W) (ox) 4 ( 1µ m) ( µ m) ( pf µ m ) g pF ( λ 0.5µm ) Uni ransisor: A ransisor ha can be convenienly conneced o meal a boh source and drain Diffusion (source and drain) capaciance d : Proporional o oal diffusion-o-subsrae juncion area 1. Base area +. he area of he ( ab ) + ( a + b ) ja jp " sidewall " periphery where 1. ja: Juncion capaciance 4 4 pf / µ m (3 10 NMOS,5 10 PMOS). jp: 4 4 Periphery capaciance pf / µ m (4 10 NMOS,4 10 PMOS) 3. a : Widh of diffusion area (µm) 4. b : engh of diffusion area (µm) 00/4/18 5

6 Thickness of depleion layer depends on he volage across he juncion, boh ja and jp are funcions of juncion volage (j) j ( a p) ( a, p) m j, jo 1 (m0.3~0.5) b j Juncion volage (negaive for reverse bias) jo(a,p) Zero-bias capaciance (j 0) b Build-in juncion poenial ~0.6 Diffusion capaciance form sb and db in Fig Rouing capaciance Rouing capaciance beween meal and poly layers and he subsrae can be modeled as a parallel-plae capaciance. ε A plus fringing field ha occurs a he edges of he conducor due o is finie hickness. Toal capaciance (a) Parallel-plae capaciance of widh (w-/) + (b) A cylindrical capaciance of radiaes (/) w π ε + h h h h ln Empirical formula w w ε h h h 00/4/18 6

7 In general, meal and poly lines have higher capaciance value han he prediced values (due o he fringing facor) Muliple conducor capaciance (Fig.4.11 and 4.1) Disribued R effecs ong wires arge R Transmission line effecs R-secion model dj d ( I I ) j 1 j ( j 1 j ) ( j j + 1) n( n + 1) R R n R (n: secion number) As number of secions increase Differenial equaions x disance from inpu d d rc r resisance per uni lengh d dx c capaciance per uni lengh x ( propagaion ime) kx ( wire of lengh x) rc 1 ( l lengh of he wire ) l Example : r 0 Ω µm, 4 c 4 10 pf µ m (a) Poly bus of -mm, 15 p 4 10 l 16ns (b) Poly bus (-mm) poly bus (1-mm) + buffer p ns + τ buf 15 ( 1000 ) + τ ( 1000 ) + 4 ns buf 8ns + τ buf 00/4/18 7

8 onusions: (a) Use poly for only local inerconnecion or very slow global inerconnecion in wo-meal process. (b) As speed increases, meal layer will also have R effec Add buffer Widen he line ( R, increases a lile ) Shoren lengh ( l ) R delay model (imporan in calculaing clock disribuion in highspeed, high-densiy chips), R : oal lumped R, of he line. τ rcl apaciance design guide (Sec.4.3.7) Wire-lengh design guide (Table 4.7) Inducance (Sec.4.4) 4.5 Swiching haracerisics Swiching speed : 1. Time o charge he load capacior oward. Time o discharge oward SS (a) Rise ime (r): Time for a waveform o rise from 10%~90% of is seady-sae value. (b) Fall ime (f): fall from 90%~10% (c) Delay ime(d): ime difference beween inpu ransiion (50%) and he 50% oupu level. 00/4/18 8

9 Fall ime ( f ) : X1: NMOS u-off X: NMOS sauraed region X3: NMOS nonsauraion (inear mode) Analysis of f IN, (gs ), (iniial value) (a) f1 ou drops from 0.9 o (-n) (X dsgs-) (sauraion) (b) f ou drops from (-n) o 0.1 (dsgs- X3) (nonsauraion, linear mode) f1 (NMOS is in sauraion mode) d d ou ( ) 0 n + n (discharge curren is consan) f 1 f n ( ) n ( n 0.1 ) ( ) n n n d ou 00/4/18 9

10 f (NMOS is in linear mode) IN DS ou I DS n ( ) ou n ou d d ou n ( ) ou n ou ln 19 0 [ n] f n ( 1 n), n n/ f f f 1 + f k ( Eq.4.37 ) n ( k 3 ~ 4) Increases speed (How o opimize MOS circui speed?) - Reduce load capaciance - Increase n - ow supply volage low speed Rise ime ( p 0.1) ( 1 p) ( 19 p) r + ln 0 p p 1 p f k p ( k 3 ~ 4) Equal size n,p devices, np f r!! f r n p W p ( ~ 3) Wn 00/4/18 10

11 Delay ime * Approximaion: r f dr df An alernaive formula (a) 1 n ( 1 n) + ln ( ) df AN, AN n 1 n 1 n 0 (AN 0.83) wih nn/, 0ou/ 0 (b) dr A p A p p 0.83 (c) Average gae delay for rising and falling ransiion av dr + df SPIE simulaion (Figure 4.0) Empirical delay model: Back subsiue ino Eqs. (4.46) & (4.47) o obain AN and AP for Wp Wn, AN AP 0.36 dr 0.36 /n Gae delays For pull-down case W n W p, µ n1 n n3 ox W 1 n neff n1 n ( ) n3 00/4/18 11

12 For pull-up case: p,eff p (only one urns on), p,eff 3p (hree urn on) For p 0.3 n r k ( 0.3 ) Mobiliy difference Graphical undersanding n, f k n 3 串聯 f r 1 Graphical Rule n series 3 W µ ox τ series k n 3 Fall ime: m n-devices in series f`m f Rise ime: m p-devices in series r`m r Fall ime: m n-devices in parallel (all urn on) f`f/m Rise ime: m p-devices in parallel (all urn on) r`r/m Swich-level R models 00/4/18 1

13 (A) Simple R model : (R, are lumped ogeher) df Σ Rpulldown Σ pulldown-pah dr (RN1+RN+ RN3+RN4) (ou+ab+ bc+cd) Rp ou Effecive Resisance R Reff (/W) (B) Penfield-Rubensein model : calculae delays in generalized R ree (ladder) Ri Summed Resisance from d Σ Ri i poin i o power or ground i apaciance a poin i df (RN1 cd)+[(rn1+rn) bc]+[(rn1+rn+rn3) ab]+[(rn1+rn+rn3+rn4) ou] Macro modeling (Daa book) Tswin: Inpu waveform in: Inpu capaciance Tbeou: Delay hrough he gae Tswou: Oupu waveform : Oupu capaciance In ASI designs, logic gaes are reaed as simple delay elemens. d inernal + k oupu Oupu delay, which is proporional o oupu loading capaciance. Fixed inernal delay. 00/4/18 13

14 SPIE Simulaion Experimens: * Parameer Example: r k.1ns f k 3.8ns ( k is in pf ) 00/4/18 14

15 Body effec (1) Body Effec: γ sb (hange in hreshold volage is a funcion of Source-o-subsrae bias volage). Beer Bad () Poin D rises o abou 1.7vols before being discharged o ground ( 上圖所示 ) (3) Nodes cd, bc, and ab are a an n-hreshold below (~3.1vols). When N1B urns on. Nodes ab,bc,and cd are pulled o ground in ha order ( 下圖所示 ) (4) When >> inernal cap, his effec can be minimized. Sraegy o handle Body effec (1) Place ransisors wih laes arriving signals neares he oupu of he gae. The early signals discharge inernal nodes, and he body effec is minimized. () Minimize inernal capaciances: If diffusion wire is used o minimize he gae geomery, ry o use i a he oupu raher han on some inernal nodes. (3) Body effec is essenially a dynamic problem involving he charging of parasiic capaciances. * onclusion of Secion 4.5: Model of ransisors and parasiic capaciances mus be accurae so ha AD ools can work well. 00/4/18 15

16 4.6 MOS-Gae Transisor Sizing * For rf, Wp(-3)Wn Increase layou area and dynamic power consumpion. *Approximaed delay for an inverer pair (a) inv-pair f + r (WpWn) R(3eq) + ( R )(3eq) 3Req +3 Req 6Req R ON Res of a uni-size ransisor eqg+d (gae and diffusion cap.) (b) inv-pair (WpWn) R(eq)+()(R)(eq) fall rise 6Req * n/p raio rise / fall inv (Inverer hreshold volage) inv dd+p+n 1+ n p n p, (Eg.4) whennp, n p invdd/ In self-loaded circuis minimum-sized devices may be used o reduce power dissipaion and increase circui packaging densiy. When he circuis have o drive any significan rouing load, his opimizaion does no apply and he n- and p- devices should be sized o yield equal rise and fall ime. 00/4/18 16

17 4.6. Sage raio (Transisor Sizing skills) * Used in applicaions of (1) ong bus () I/O Buffers (3) Pads (4) Off-chip capaciive load To minimize he delay beween inpu and oupu while minimizing he area and power dissipaion. d: he average delay of a minimum-sized inverer driving anoher minimum-sized inverer. Delay of each sage (d ): R R/a, a d a d n-sage n(a d ) Toal delay /gra n ( produc of n sages) n lnr lna Toal delay lnr lna a d (Noe ha lnr, d are consans) Minimum delay ae (.714) 00/4/18 17

18 4.7 Power dissipaion MOS power sources: (1) Ps: Saic dissipaions (leakage curren) () Pd: Dynamic dissipaions - Swiching ransien curren from dd o GND. - The Energy/power o charge and discharge Saic Power Dissipaion >No curren > Ps0, Reverse-biased parasiic diodes (leakage curren) eakage curren : i o is (e qv /KT -1) 0.1nA~0.5nA per device a room emperaure. where is: Reverse sauraion curren v: Diode volage Ps n leakage curren x supply volage, 1 where n oal device number 00/4/18 18

19 4.7. Dynamic Power Dissipaion 0 1,1 0 n,p devices are boh on Shor circui curren pulse from dd o ss As he increases, he discharge or charge currens sar o dominae he curren drawn from he power suppliers. 00/4/18 19

20 ** Dynamic Power Dissipaion: harge/discharge *Pd 1 p/ p in() ou d + 1 p 0 p ip() (dd-ou) d p/ in() n-device ransien curren dou d ip() p-device ransien curren d(dd-ou) d Pd Average dynamic power o charge/discharge Pd dd p ou dou + 0 p (dd-ou) d(dd-ou) 0 dd dd / p dd fp 00/4/18 0

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22 4.7.3 Shor-circui dissipaion PscImean * dd I mean [ 1 T 1 3 I() d + 1 T I() d ] Assume ha n-p, ßnßpß Imean * T (in()-) d 1 wih 1. in() dd r * (linear approximaion). 1 dd * r, r,(rfrf) (NMOS urn on) Psc rf 1 (dd-)3 p Funcions of ß, r, f of inpu waveform. * P oal Ps+Pd+Psc Percenage of aciviy * oal * dd p (Simulaor) (AD ool) I * R oal-swich * dd Toal-no-of-cycles * p * Power economy (achieve low-power and low-energy MOS designs) -Reduce leakage (use complemenary logic + minimize diffusion area) -dd (dd ) : mos effecive. - (design) and f clk (no desirable) -Noe ha dd --> Speed (r,f ) 00/4/18

23 4.9 harge Sharing -Bus is modeled as a capacior b Qbb* b, Qss * s Toal charge: Q T Qb+Qs b*b+s*s Toal capaciance: T b+s (when swich is closed) 4.11 Yield R Q T b*b+s*s T b+s If bdd, b>>s b R dd [ b+s ] (Why?) To make reliable ransfer from b o s,s<<b (In general, b> 10 s) Problem involving charge sharing occurs in dynamic logic gae designs (haper 5.) Funcion of (1) Technology () hip area (3) ayou Yield(Y) No. of oal chip on wafer Toal no. of chips x 100% (a) Y e AD Achip area (Seed s model) Ddefec densiy (lehal defecs per cm ) (for large chip and Y<30%) -AD 1- e (b) Y[ AD ], for small chips & Y>30% (Murphy s model) (c) Yield decreases significanly as chip area in increased!! 00/4/18 3