MC74HC138A. 1 of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
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1 of 8 Decoder/ Demuliplexer High Performance Silicon Gae CMOS The is idenical in pinou o he LS8. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus. The HC8A decodes a hree bi Address o one of eigh acive low oupus. This device feaures hree Chip Selec inpus, wo acive low and one acive high o faciliae he demuliplexing, cascading, and chip selecing funcions. The demuliplexing funcion is accomplished by using he Address inpus o selec he desired device oupu; one of he Chip Selecs is used as a daa inpu while he oher Chip Selecs are held in heir acive saes. PDIP N SUFFIX CASE 68 MARKING DIAGRAMS N AWLYYWWG Feaures Oupu Drive Capabiliy: 0 LSTTL Loads Oupus Direcly Inerface o CMOS, NMOS and TTL Operaing olage Range:.0 o 6.0 Low Inpu Curren:.0 A High Noise Immuniy Characerisic of CMOS Devices In Compliance wih he Requiremens Defined by JEDEC Sandard No. 7A Chip Complexiy: 00 FETs or 9 Equivalen Gaes Pb Free Packages are Available* SOIC D SUFFIX CASE 75B TSSOP DT SUFFIX CASE 98F HC8AG AWLYWW HC 8A ALYW SOEIAJ F SUFFIX CASE 966 7HC8A ALYWG A = Assembly Locaion L, WL = Wafer Lo Y, YY = Year W, WW = Work Week G = Pb Free Package = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering and shipping informaion in he package dimensions secion on page of his daa shee. *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. Semiconducor Componens Indusries, LLC, 005 Publicaion Order Number: /D
2 A0 A A 5 Y0 Y CS Y CS 5 Y CS Y Y Y5 GND 8 9 Y6 Figure. Pin Assignmen ADDRESS INPUTS A0 A A 6 CS CHIP SELECT CS INPUTS 5 CS 5 0 Y0 Y Y Y Y Y5 9 7 Y6 Y7 PIN = PIN 8 = GND Figure. Logic Diagram ACTIE LOW OUTPUTS Inpus FUNCTION TABLE Oupus CSCS CS A A A0 Y0 Y Y Y Y Y5 Y6 Y7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = high level (seady sae); L = low level (seady sae); X = don care ORDERING INFORMATION Device Package Shipping N PDIP 500 Unis / Rail NG PDIP 500 Unis / Rail D SOIC 8 Unis / Rail DG SOIC 8 Unis / Rail DR SOIC 500 Tape & Reel DRG SOIC 500 Tape & Reel DTR TSSOP * 500 Tape & Reel DTRG TSSOP * 500 Tape & Reel F SOEIAJ 50 Unis / Rail FG SOEIAJ 50 Unis / Rail FEL SOEIAJ 000 Tape & Reel FELG SOEIAJ 000 Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. *This package is inherenly Pb Free.
3 MAXIMUM RATINGS SymbolÎÎ Parameer alue Uni ÎÎ DC Supply olage (Referenced o GND) 0.5 o in ÎÎ DC Inpu olage (Referenced o GND) 0.5 o ou ÎÎ DC Oupu olage (Referenced o GND) 0.5 o I in ÎÎ DC Inpu Curren, per Pin ± 0 ma I ou ÎÎ DC Oupu Curren, per Pin ± 5 ma I CC ÎÎ DC Supply Curren, and GND Pins ± 50 ma P D ÎÎ Power Dissipaion in Sill Air, Plasic DIP 750 mw SOIC Package 500 Î TSSOP Package 50 T sg ÎÎ Sorage Temperaure 65 o + 50 C T L ÎÎ Lead Temperaure, mm from Case for 0 Seconds ÎÎ C Î (Plasic DIP, SOIC or TSSOP Package) 60 Maximum raings are hose values beyond which device damage can occur. Maximum raings applied o he device are individual sress limi values (no normal operaing condiions) and are no valid simulaneously. If hese limis are exceeded, device funcional operaion is no implied, damage may occur and reliabiliy may be affeced. Deraing Plasic DIP: 0 mw/ C from 65 o 5 C SOIC Package: 7 mw/ C from 65 o 5 C TSSOP Package: 6..W/ C from 65 o 5 C For high frequency or heavy load consideraions, see Chaper of he ON Semiconducor High Speed CMOS Daa Book (DL9/D). RECOMMENDED OPERATING CONDITIONS ÎÎ Symbol Parameer Min Max Uni DC Supply olage (Referenced o GND) in, ou DC Inpu olage, Oupu olage (Referenced o GND) 0 T A Operaing Temperaure, All Package Types C r, f ÎÎ Inpu Rise and Fall Time ÎÎ = ns Î (Figure ) = Î CC = ÎÎ DC ELECTRICAL CHARACTERISTICS (olages Referenced o GND) Î SymbolÎÎ Parameer ÎÎ Tes Condiions Guaraneed Limi CC 55 C o 5 C 85 C 5 C Uni IH ÎÎ Minimum High Level Inpu ÎÎ ou = 0. or olage Î ou 0 A IL ÎÎ Maximum Low Level Inpu ÎÎ ou = 0. or olage Î ou 0 A OH ÎÎ Minimum High Level Oupu ÎÎ in = IH or IL olage Î ou 0 A Î in = IH or IL ou. ma ÎÎ Î ou.0 ma Î ou 5. ma This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, in and ou should be consrained o he range GND ( in or ou ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher GND or ). Unused oupus mus be lef open
4 OL ÎÎ Maximum Low Level Oupu ÎÎ in = IH or IL ÎÎ Î olage ÎÎ ou 0 A Î in = IH or IL ou. ma ou.0 ma Î ou 5. ma I in Maximum Inpu Leakage ÎÎ ÎÎ in = or GND 6.0 ± 0. ±.0 ±.0 Î A Curren I CC ÎÎ ÎÎ Maximum Quiescen Supply in = or GND Î Curren (per Package) ÎÎ I ou = 0 A 6.0 ÎÎ 0 0 A NOTE: Informaion on ypical parameric values can be found in Chaper of he ON Semiconducor High Speed CMOS Daa Book (DL9/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Inpu r = f = 6.0 ns) Î Symbol Parameer Guaraneed Limi CC 55 C o 5 C 85 C 5 C Uni PLH, Maximum Propagaion Delay, Inpu A o Oupu Y ns PHL (Figures and ) PLH, Maximum Propagaion Delay, CS o Oupu Y ns PHL (Figures and ) PLH, Maximum Propagaion Delay, CS or CS o Oupu Y ns PHL (Figures and ) TLH, Maximum Oupu Transiion Time, Any Oupu ns THL (Figures and ) C in Maximum Inpu Capaciance pf NOTE: For propagaion delays wih loads oher han 50 pf, and informaion on ypical parameric values, see Chaper of he ON Semiconducor High Speed CMOS Daa Book (DL9/D). 5 C, = 5.0 C PD Power Dissipaion Capaciance (Per Package)* 55 pf * Used o deermine he no load dynamic power consumpion: P D = C PD CC f + I CC. For load consideraions, see Chaper of he ON Semiconducor High Speed CMOS Daa Book (DL9/D).
5 PACKAGE DIMENSIONS PDIP N SUFFIX CASE ISSUE T A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: INCH.. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F S C K T SEATING PLANE D PL 0.5 (0.00) M T A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC.5 BSC H BSC.7 BSC J K L M S SOIC D SUFFIX CASE 75B 05 ISSUE J A 9 8 B P 8 PL 0.5 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.7 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D PL 0.5 (0.00) M T B S A S M R X 5 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.7 BSC BSC J K M P R
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8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
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