Quad 2-Input OR Gate High-Performance Silicon-Gate CMOS
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- Bathsheba Chase
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1 TECNICAL DATA Quad 2-Inpu OR ae igh-performance Silicon-ae CMOS The is idenical in pinou o he LS/ALS32. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LS/ALSTTL oupus. Oupus Direcly Inerface o CMOS, NMOS, and TTL Operaing Range: 2. o 6. Low Inpu Curren:. µa igh Noise Immuniy Characerisic of CMOS Devices N SUFFIX PLASTIC DIP D SUFFIX SOIC ORDERIN INFORMATION N Plasic DIP D SOIC T A = -55 o 25 C for all packages LOIC DIARAM PIN ASSINMENT FUNCTION TABLE PIN = PIN 7 = ND Inpus Oupu A B Y L L L L L L LOW volage level I volage level
2 MAXIMUM RATINS * Symbol Parameer alue Uni DC Supply (Referenced o ND) -.5 o +7. IN DC Inpu (Referenced o ND) -.5 o +.5 OUT DC Oupu (Referenced o ND) -.5 o +.5 I IN DC Inpu Curren, per Pin ±2 ma I OUT DC Oupu Curren, per Pin ±25 ma I CC DC Supply Curren, and ND Pi ±5 ma P D Power Dissipaion in Sill Air, Plasic DIP+ SOIC Package+ Tsg Sorage Temperaure -65 o +5 C T L Lead Temperaure, mm from Case for Seconds (Plasic DIP or SOIC Package) 75 5 * Maximum Raings are hose values beyond which damage o he device may occur. Funcional operaion should be resriced o he Recommended Operaing Condiio. +Deraing - Plasic DIP: - mw/ C from 65 o 25 C SOIC Package: : - 7 mw/ C from 65 o 25 C mw 26 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameer Min Max Uni DC Supply (Referenced o ND) IN, OUT DC Inpu, Oupu (Referenced o ND) T A Operaing Temperaure, All Package Types C r, f Inpu Rise and Fall Time (Figure ) =2. = = This device conai proecion circuiry o guard agai damage due o high saic volages or elecric fields. owever, precauio mus be aken o avoid applicaio of any volage higher han maximum raed volages o his high-impedance circui. For proper operaion, IN and OUT should be corained o he range ND ( IN or OUT ). Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher ND or ). Unused oupus mus be lef open.
3 DC ELECTRICAL CARACTERISTICS (s Referenced o ND) Symbol Parameer Tes Condiio -55 C o 25 C I Minimum igh- Level Inpu IL Maximum Low - Level Inpu O Minimum igh- Level Oupu OUT = -. I OUT 2 µa OUT =. or -. I OUT 2 µa IN = I or IL I OUT 2 µa uaraneed Limi 85 C 25 C Uni IN = I or IL I OUT 4. ma I OUT 5.2 ma OL Maximum Low- Level Oupu IN = IL I OUT 2 µa I IN I CC Maximum Inpu Leakage Curren Maximum Quiescen Supply Curren (per Package) IN = IL I OUT 4. ma I OUT 5.2 ma IN = or ND 6. ±. ±. ±. µa IN = or ND I OUT =µa µa
4 AC ELECTRICAL CARACTERISTICS (C L =5 pf,inpu r = f =6., I =, IL = ) Symbol Parameer -55 C o 25 C PL, PL TL, TL Maximum Propagaion Delay, Inpu A or B o Oupu Y (Figures and 2) Maximum Oupu Traiion Time, Any Oupu (Figures and 2) uaraneed Limi 85 C 25 C Uni C IN Maximum Inpu Capaciance - pf C PD Power Dissipaion Capaciance (Per ae) Used o deermine he no-load dynamic power coumpion: P D =C PD 2 f+i CC C, =5. 2 pf INPUT A or B OUTPUT Y PL r 9% 5% % 9% 5% % f PL ND DEICE UNDER TEST OUTPUT TEST POINT C L * TL TL Figure. Swiching Waveforms * Includes all probe and jig capaciance Figure 2. Tes Circui EXPANDED LOIC DIARAM (/4 of he Device)
5 N SUFFIX PLASTIC DIP (MS - AA) NOTES: A F.25 (.) M T. Dimeio A, B do no include mold flash or prorusio. Maximum mold flash or prorusio.25 mm (.) per side. 8 7 D N B -T- SEATIN 5.27 PLANE K D M J F J 8.25 (.) M T C M NOTES: K..25. Dimeio A and B do no include mold flash or prorusion. M Maximum mold flash or prorusion.5 mm (.6) per side P for A; for B.25 mm (.) per side. R.25.5 C -T- K SEATIN PLANE M L J Dimeion, mm Symbol MIN MAX A B C 5.33 D F J K L M.2.36 N.38 D SUFFIX SOIC (MS - 2AB) A 8 7 B P C Symbol MIN MAX A B C D.33.5 F.4.27 R x 45 Dimeion, mm.27
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