MC14175BFELG. Quad Type D Flip Flop

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1 MC475B Quad Type D FlipFlop The MC475B quad ype D flipflop is coruced wih MOS Pchannel and Nchannel enhancemen mode devices in a single monolihic srucure. Each of he four flipflops is posiiveedge riggered by a common clock inpu (C). An acivelow rese inpu (R) asynchronously reses all flipflops. Each flipflop has independen Daa (D) inpus and complemenary oupus (Q and Q). These devices may be used as shif regiser elemens or as ype T flipflops for couner and oggle applicaio. Feaures Complemenary Oupus Saic Operaion All Inpus and Oupus Buffered Diode Proecion on All Inpus Supply Volage Range = 3.0 Vdc o 8 Vdc Oupu Compaible wih Two LowPower TTL Loads or One LowPower Schoky TTL Load Funcional Equivalen o TTL 7475 PbFree Packages are Available* MAXIMUM RATINGS olages Referenced o V SS ) Parameer Symbol Value Uni DC Supply Volage Range V DD 0.5 o +8.0 V Inpu or Oupu Volage Range (DC or Traien) Inpu or Oupu Curren (DC or Traien) per Pin V in, V ou 0.5 o V DD I in, I ou ±0 ma Power Dissipaion per Package (Noe ) P D 500 mw Ambien Temperaure Range T A 55 o +25 C Sorage Temperaure Range 65 o +50 C Lead Temperaure (8Second Soldering) 260 C Sresses exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiio is no implied. Exended exposure o sresses above he Recommended Operaing Condiio may affec device reliabiliy.. Temperaure Deraing: Plasic P and D/DW Packages: 7.0 mw/ C From 65 C To 25 C This device conai proecion circuiry o guard agai damage due o high saic volages or elecric fields. However, precauio mus be aken o avoid applicaio of any volage higher han maximum raed volages o his highimpedance circui. For proper operaion, V in and V ou should be corained o he range V SS in or V ou ) V DD. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher V SS or V DD ). Unused oupus mus be lef open. V ORDERING INFORMATION Device Package Shipping MC475BCP PDIP6 25 Unis/Rail MC475BCPG MC475BD SOIC6 48 Unis/Rail MC475BDG MC475BDR2 SOIC6 2500/Tape & Reel MC475BDR2G MC475BFEL hp://oemi.com PDIP6 P SUFFIX CASE SOIC6 D SUFFIX CASE 75B SOEIAJ6 F SUFFIX CASE 966 A = Assembly Locaion WL, L = Wafer Lo YY, Y = Year WW, W = Work Week G = PbFree Package PDIP6 (PbFree) SOIC6 (PbFree) SOIC6 (PbFree) SOEIAJ6 6 6 MARKING DIAGRAMS MC475BCP AWLYYWWG 475BG AWLYWW MC475B ALYWG 25 Unis/Rail 48 Unis/Rail 2500/Tape & Reel 2000/Tape & Reel MC475BFELG SOEIAJ6 (PbFree) 2000/Tape & Reel *For addiional informaion on our PbFree sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. For informaion on ape and reel specificaio, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaio Brochure, BRD80/D. Semiconducor Componens Indusries, LLC, 2006 June, 2006 Rev. 6 Publicaion Order Number: MC475B/D

2 MC475B TRUTH TABLE R D0 V SS Figure. Pin Assignmen 9 V DD Inpus Oupus Clock Daa Rese Q Q X Q Q X X 0 0 X = Don Care D Q Q D3 D2 C No Change CLOCK RESET D0 D D2 D3 Q Q V DD = PIN 6 V SS = PIN 8 Figure 2. Block Diagram Figure 3. Timing Diagram Figure 4. Funcional Block Diagram hp://oemi.com 2

3 MC475B ELECTRICAL CHARACTERISTICS olages Referenced o V SS ) Î 55 C 25 C ÎÎ 25 C V DD ÎÎ TypÎ Characerisic Symbol Vdc ÎÎ Min Max Min (Noe 2) Max Min Î Max Uni Oupu Volage 0 Level V Î V in = V DD or 0 Î OL Vdc Î 0 Î Î 0 Î Level Î V in = 0 or V DD Î V OH 4.95 Î 4.95 Î 4.95 Vdc Î Î 4.95 Î Inpu Volage 0 Level Î V IL ÎÎ Vdc Î O = 4.5 or 0.5 Vdc) O = 9.0 or.0 Vdc) 0 3.0Î 4.50Î Î O = 3.5 or.5 Vdc) 5 4.0Î 6.75Î Level Î O = 0.5 or 4.5 Vdc) Î V IH ÎÎ Vdc Î O =.0 or 9.0 Vdc) O =.5 or 3.5 Vdc) Î Î Oupu Drive Curren I Î OH = 2.5 Vdc) Source Î OH madc 3.0 Î Î.7 Î OH = 4.6 Vdc) OH = 9.5 Vdc) Î OH = 3.5 Vdc) Î 2.4 Î OL = 0.4 Vdc) Sink OL = 0.5 Vdc) Î I OL 0.64 Î Î 0.36 madc Î OL =.5 Vdc) Î Î 2.4 Î Inpu Curren Î I in 5 ± 0.Î ±0.0000Î ± 0. ±.0 Adc Î Inpu Capaciance Î C in Î in = 0) Î Î 7.5 pf Quiescen Curren I Î (Per Package) Î DD Adc 0 0Î 0.00Î Î 0.05Î Î Toal Supply Curren (Noe 3, 4) Î I T ÎÎ I T = (.7 A/kHz) f + I DD Adc (Dynamic plus Quiescen, 0 I Î Per Package) 5 ÎÎ T = (3.4 A/kHz) f + I DD I T = ( A/kHz) f + I DD (C Î L = 50 pf on all oupus, all buffers swiching) 2. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance. 3. The formulas given are for he ypical characerisics only a 25 C. 4. To calculae oal supply curren a loads oher han 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in A (per package), C L in pf, V = DD V SS ) in vols, f in khz is inpu frequency, and k = hp://oemi.com 3

4 MC475B SWITCHING CHARACTERISTICS (Noe 5) (C L = 50 pf, T A = 25 C) Î All Types V DD Î Typ Characerisic Symbol Vdc Min (Noe 6) Max Uni Oupu Rise and Fall Time TLH, THL Î TLH, THL = (.35 /pf) C L + 32 Î Î Î TLH, THL = (0.6 /pf) C L TLH, THL = (0.4 /pf) C L + 20 Î Î 5 Î Propagaion Delay Time Clock o Q, Q Î PLH, PHL Î PLH, PHL = (0.9 /pf) C L PLH, PHL = (0.36 /pf) C L + 72 Î Î 0 Î PLH, PHL = (0.26 /pf) C L Î Î Propagaion Delay Time Rese o Q, Q PHL = (0.9 /pf) C L Î PHL, PLH PHL = (0.36 /pf) C L + 2 PHL = (0.26 /pf) C L Î Î Î Î Clock Pulse Widh Î WH Î 250 Î Î Rese Pulse Widh WL Î Î Clock Pulse Frequency f cl Î Î 2.0 mhz Clock Pulse Rise and Fall Time TLH, THL Î 0 Î 5 s Daa Seup Time su Î 0 50 Î Daa Hold Time h Î Î Rese Removal Time rem Î The formulas given are for he ypical characerisics only a 25 C. 6. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance hp://oemi.com 4

5 MC475B PACKAGE DIMENSIONS PDIP6 CASE ISSUE T A B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D 6 PL S C K 0.25 (0.00) M T SEATING T PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S SOIC6 CASE 75B05 ISSUE J A B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D 6 PL 0.25 (0.00) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R hp://oemi.com 5

6 MC475B PACKAGE DIMENSIONS SOEIAJ6 CASE 9660 ISSUE A e 6 9 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P M L E Q L DETAIL P c NOTES: М. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 982. М 2. CONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, coequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaio can and do vary in differen applicaio and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any licee under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaio inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agai all claims, coss, damages, and expees, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@oemi.com N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: hp://oemi.com 6 ON Semiconducor Websie: Order Lieraure: hp:// For addiional informaion, please conac your local Sales Represenaive MC475B/D

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