SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY

Transcription

1 Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the true (non-inverted) form. The LS57 can also be used to generate any four of the different functions of two variables. The LS57 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. Schottky Process for High Speed Multifunction Capability Non-Inverting Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I OH Output Current High 0.4 ma I OL Output Current Low 8.0 ma LOW POWER SCHOTTKY PLASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 75B SOEIAJ M SUFFIX CASE 966 ORDERING INFORMATION Device Package Shipping N Pin DIP 2000 Units/Box D SOIC 38 Units/Rail DR2 SOIC 2500/Tape & Reel M SOEIAJ See Note MEL SOEIAJ See Note. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2006 June, 2006 Rev. 9 Publication Order Number: /D

2 V CC E I 0c I c Z c I 0d I d Zd NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package S I 0a I a Z a I 0b I b Z b GND LOADING (Note a) PIN NAMES HIGH LOW S E I 0a I 0d I a I d Z a Z d Common Select Input Enable (Active LOW) Input Data Inputs from Source 0 Data Inputs from Source Multiplexer Outputs.0 U.L..0 U.L. 0 U.L U.L U.L. 5 U.L. NOTES: a) TTL Unit Load (U.L.) = 40 A HIGH/.6 ma LOW. Figure. Connection Diagram DIP (TOP VIEW) EI 0a I a I 0b I b I 0c I c I 0d I d S Z a Z b Z c Z d V CC = PIN GND = PIN 8 Figure 2. Logic Symbol 2

3 V CC = PIN GND = PIN 8 = PIN NUMBERS Figure 3. Logic Diagram FUNCTIONAL DESCRIPTION The LS57 is a Quad 2-Input Multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four bits of data from two sources under the control of a common Select Input (S). The Enable Input (E) is active LOW. When E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The LS57 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. The logic equations for the outputs are: Z a = E (I a S + I 0a S) Z b = E (I b S + I 0b S) Z c = E (I c S + I 0c S) Z d = E (I d S + I 0d S) A common use of the LS57 is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select Input. A less obvious use is as a function generator. The LS57 can generate any four of the different functions of two variables with one variable common. This is useful for implementing highly irregular logic. TRUTH TABLE ENABLE SELECT INPUT INPUTS OUTPUT E S I 0 I Z H X X X L L H X L L L H X H H L L L X L L L H X H H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care 3

4 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Min Typ Max V IH Input HIGH Voltage 2.0 V V IL Input LOW Voltage 0.8 Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp Diode Voltage V V CC = MIN, I IN = 8 ma V OH Output HIGH Voltage V V OL I IH I IL Output LOW Voltage Input HIGH Current I 0, I E, S I 0, I E, S Input LOW Current I 0, I E, S V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V I OL = 4.0 ma V CC = V CC MIN, V IN = V IL or V IH V I OL = 8.0 ma per Truth Table I OS Short Circuit Current (Note 2) ma V CC = MAX I CC Power Supply Current ma V CC = MAX 2. Not more than one output should be shorted at a time, nor for more than second. μa ma ma V CC = MAX, V IN = 2.7 V V CC = MAX, V IN = 7.0 V V CC = MAX, V IN = 0.4 V AC CHARACTERISTICS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditions Propagation Delay Data to Output ns Figure 2 Propagation Delay Enable to Output ns Figure V CC = 5.0 V C L = 5 pf Propagation Delay Select to Output ns Figure 2 AC WAVEFORMS V IN.3 V.3 V V IN.3 V.3 V V OUT.3 V.3 V V OUT.3 V.3 V Figure. Figure 2. 4

5 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE ISSUE R H A 8 G F 9 D PL B S C K 0.25 (0.00) M T T SEATING PLANE A M J L M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S

6 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 75B 05 ISSUE J T SEATING PLANE 9 8 G A K B D PL 0.25 (0.00) M T B S A S P 8 PL 0.25 (0.00) M B S C M R X 45 J F NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R

7 PACKAGE DIMENSIONS M SUFFIX SOEIAJ PACKAGE CASE ISSUE O e 9 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P M L E Q L DETAIL P c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 53, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative /D