MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop

Transcription

1 Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the traition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be traferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S D (Set) sets Q to HIGH level LOW input to C D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C D and S D makes both Q and Q HIGH Features Outputs Source/Sink 24 ma ACT74 Has TTL Compatible Inputs Pb Free Packages are Available CC C D2 D 2 CP 2 S D2 Q 2 Q C D S D2 D Q CP 2 Q2 CP S D Q D 2 CD2 Q PDIP 4 N SUFFIX CASE 646 SOIC 4 D SUFFIX CASE 75A TSSOP 4 DT SUFFIX CASE 948G SOEIAJ 4 M SUFFIX CASE 965 ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 7 of this data sheet C D D CP S D Q Q GND Figure. Pinout: 4 Lead Packages Conductors (Top iew) PIN ASSIGNMENT PIN D, D 2 CP, CP 2 C D, C D2 S D, S D2 Q, Q, Q 2, Q 2 FUNCTION Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs Semiconductor Components Industries, LLC, 2006 October, 2006 Rev. 7 Publication Order Number: MC74AC74/D

2 TRUTH TABLE (Each Half) NOTE: Inputs Outputs S D C D CP D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q 0 Q 0 H = HIGH oltage Level L = LOW oltage Level X = Immaterial; = LOW-to-HIGH Clock Traition Q 0 (Q 0 ) = Previous Q(Q) before LOW-to-HIGH Traition of Clock D D CP D Q 2 S D2 D 2 CP 2 Q 2 CD 2 Figure 2. Logic Symbol S D D Q CP Q C D NOTE: This diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays. Figure 3. Logic Diagram MAXIMUM RATINGS Symbol Parameter alue CC DC Supply oltage (Referenced to GND) 0.5 to +7.0 in DC Input oltage (Referenced to GND) 0.5 to CC +0.5 out DC Output oltage (Referenced to GND) 0.5 to CC +0.5 I in DC Input Current, per Pin ±20 ma I out DC Output Sink/Source Current, per Pin ±50 ma I CC DC CC or GND Current per Output Pin ±50 ma T stg Storage Temperature 65 to +50 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. 2

3 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max CC Supply oltage AC ACT in, out DC Input oltage, Output oltage (Ref. to GND) 0 CC t r, t f Input Rise and Fall Time (Note ) AC Devices except Schmitt Inputs t r, t f Input Rise and Fall Time (Note ) ACT Devices except Schmitt Inputs / T J Junction Temperature (PDIP) 40 C T A Operating Ambient Temperature Range C I OH Output Current High 24 ma I OL Output Current Low 24 ma. in from 30% to 70% CC ; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. in from 0.8 to 2.0 ; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS IH IL Symbol Parameter OH Minimum High Level Input oltage Maximum Low Level Input oltage Minimum High Level Output oltage CC () 74AC T A = +25 C Typ 74AC T A = 40 C to +85 C Guaranteed Limits / Conditio OUT = or CC OUT = or CC I OUT = 50 A OL Maximum Low Level Output oltage * IN = IL or IH ma I OH 24 ma ma I OUT = 50 A I IN Maximum Input Leakage Current * IN = IL or IH ma I OL 24 ma ma 5.5 ±0. ±.0 A I = CC, GND I OLD Minimum Dynamic ma OLD =.65 Max I OHD Output Current ma OHD = 3.85 Min I CC Maximum Quiescent Supply Current A IN = CC or GND *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: I IN and I 3.0 are guaranteed to be less than or equal to the respective 5.5 CC. 3

4 AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL38/D) Symbol f max t PLH t PHL t PLH t PHL Maximum Clock Frequency Parameter CC * () 74AC T A = +25 C 74AC T A = 40 C to +85 C Min Typ Max Min Max C Dn or S Dn to Q n or Q n C Dn or S Dn to Q n or Q n C Pn to Q n or Q n C Pn to Q n or Q n *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. MHz Fig. No AC OPERATING REQUIREMENTS Symbol Parameter CC * () Typ 74AC T A = +25 C 74AC T A = 40 C to +85 C Guaranteed Minimum Set-up Time, HIGH or LOW t s D n to CP n Hold Time, HIGH or LOW t h D n to CP n C Pn or C Dn or S Dn t w Pulse Width Recovery TIme t rec C Dn or S Dn to CP *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. Fig. No

5 DC CHARACTERISTICS IH IL Symbol Parameter OH Minimum High Level Input oltage Maximum Low Level Input oltage Minimum High Level Output oltage CC () 74ACT T A = +25 C Typ 74ACT T A = 40 C to +85 C Guaranteed Limits Conditio OUT = or CC OUT = or CC I OUT = 50 A OL Maximum Low Level Output oltage * IN = IL or IH ma I OH 24 ma I OUT = 50 A I IN Maximum Input Leakage Current * IN = IL or IH ma I OL 24 ma 5.5 ±0. ±.0 A I = CC, GND I CCT Additional Max. I CC /Input ma I = CC 2. I OLD Minimum Dynamic ma OLD =.65 Max I OHD Output Current ma OHD = 3.85 Min I CC Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time A IN = CC or GND AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL38/D) Symbol f max t PLH t PHL t PLH t PHL Maximum Clock Frequency Parameter CC * () 74ACT T A = +25 C 74ACT T A = 40 C to +85 C Min Typ Max Min Max Fig. No MHz 3 3 C Dn or S Dn to Q n or Q n C Dn or S Dn to Q n or Q n C Pn to Q n or Q n C Pn to Q n or Q n *oltage Range 5.0 is 5.0 ±0.5. 5

6 AC OPERATING REQUIREMENTS Symbol Parameter t s Set-up Time, HIGH or LOW D n to CP n t h Hold Time, HIGH or LOW D n to CP n CC * () Typ 74ACT T A = +25 C 74ACT T A = 40 C to +85 C Guaranteed Minimum Fig. No t w C Pn or C Dn or S Dn Pulse Width t rec Recovery TIme C Dn or S Dn to CP *oltage Range 5.0 is 5.0 ± CAPACITANCE Symbol Parameter alue Typ Test Conditio C IN Input Capacitance 4.5 pf CC = 5.0 C PD Power Dissipation Capacitance 35 pf CC = 5.0 6

7 ORDERING INFORMATION Device Package Shipping MC74AC74N MC74AC74NG MC74ACT74N MC74ACT74NG MC74AC74D MC74AC74DG MC74AC74DR2 MC74AC74DR2G MC74ACT74D MC74ACT74DG MC74ACT74DR2 MC74ACT74DR2G PDIP 4 PDIP 4 PDIP 4 PDIP 4 SOIC 4 SOIC 4 SOIC 4 SOIC 4 SOIC 4 SOIC 4 SOIC 4 SOIC 4 25 s/rail 55 s/rail 2500/Tape & Reel 55 s/rail 2500/Tape & Reel MC74AC74DT TSSOP 4* 96 s/rail MC74AC74DTR2 MC74AC74DTR2G TSSOP 4* TSSOP 4* 2500/Tape & Reel MC74ACT74DT TSSOP 4* 96 s/rail MC74ACT74DTR2 MC74ACT74DTR2G MC74AC74MEL MC74AC74MELG MC74ACT74MEL MC74ACT74MELG TSSOP 4* TSSOP 4* SOEIAJ 4 SOEIAJ 4 SOEIAJ 4 SOEIAJ /Tape & Reel 2000/Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 7

8 MARKING DIAGRAMS PDIP 4 SOIC 4 TSSOP 4 MC74AC74N AWLYYWWG 4 AC74G AWLYWW AC 74 ALYW SOEIAJ 4 74AC74 ALYWG MC74ACT74N AWLYYWWG 4 ACT74G AWLYWW ACT 74 ALYW 74ACT74 ALYWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) 8

9 PACKAGE DIMENSIONS PDIP 4 CASE ISSUE P B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G D 4 PL M N (0.005) M 9

10 SOIC 4 CASE 75A 03 ISSUE H T SEATING PLANE G A 4 8 D 4 PL 7 B K P 7 PL C 0.25 (0.00) M T B S A S 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.27 BSC BSC J K M P R SOLDERING FOOTPRINT* 4X X X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0

11 PACKAGE DIMENSIONS TSSOP 4 CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S S N (0.00) M B U 7 A G H N J J F DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 4X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

12 SOEIAJ 4 CASE ISSUE A L E 4 8 Q E H E M 7 L Z DETAIL P D IEW P e A c b A 0.3 (0.005) M 0.0 (0.004) NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74AC74/D