74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
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1 Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device coists of two D flip flops with individual Set, Reset, and Clock inputs. Information at a D input is traferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip flop. The Set and Reset inputs are asynchronous. Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. A Requirements ESD Performance: HBM 00 ; Machine Model 0 Chip Complexity: 28 FETs or 32 Equivalent Gates Pb Free Packages are Available SOIC 4 D SUFFIX CASE A TSSOP 4 DT SUFFIX CASE 948G MARKING DIAGRAMS 4 HC4G AWLYWW HC 4 ALYW HC4 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 4 of this data sheet. Semiconductor Components Industries, LLC, 0 February, 0 Rev. 0 Publication Order Number: 4HC4/D
2 PIN ASSIGNMENT LOGIC DIAGRAM RESET 4 RESET DATA SET Q Q FUNCTION TABLE Inputs Outputs Set Reset Clock Data Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X No Change H H H X No Change H H X No Change RESET 2 DATA 2 2 SET 2 DATA SET RESET 2 DATA 2 2 SET PIN 4 = PIN = Q Q *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. MAXIMUM RATINGS Symbol Parameter alue Unit DC Supply (Referenced to ) 0.5 to +.0 in DC Input (Referenced to ) 0.5 to out DC Output (Referenced to ) 0.5 to I in DC Input Current, per Pin ± ma I out DC Output Current, per Pin ±25 ma I CC DC Supply Current, and Pi ±50 ma P D Power Dissipation in Still Air, SOIC Package mw TSSOP Package 450 T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds C (SOIC or TSSOP Package) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. Derating SOIC Package: mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply (Referenced to ) in, out DC Input, Output (Referenced to ) 0 T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time = (Figures, 2, 3) = = = This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. 2
3 DC ELECTRICAL CHARACTERISTICS (s Referenced to ) Guaranteed Limit Symbol Parameter Test Conditio () 55 to 25 C 85 C 25 C Unit IH Minimum High Level Input out = 0. or IL Maximum Low Level Input out = 0. or OH OL Minimum High Level Output Maximum Low Level Output I out 2.4 ma I out 4.0 ma I out 5.2 ma I out 2.4 ma I out 4.0 ma I out 5.2 ma I in Maximum Input Leakage Current in = or ±0. ±.0 ±.0 A I CC Maximum Quiescent Supply Current (per Package) in = or I out = 0 A 80 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = ) Symbol f max t PLH, t PLH, t TLH, t THL Parameter Maximum Clock Frequency ( Duty Cycle) (Figures and 4) Maximum Propagation Delay, Clock to Q or Q (Figures and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures and 4) () Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 25 C, = 5.0 C PD Power Dissipation Capacitance (Per Flip Flop)* 32 pf * Used to determine the no load dynamic power coumption: P D = C PD 2 CC f + I CC. For load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D) Unit MHz 3
4 TIMING REQUIREMENTS (Input t r = t f = ) Guaranteed Limit Symbol Parameter () 55 to 25 C 85 C 25 C Unit t su Minimum Setup Time, Data to Clock (Figure 3) t h Minimum Hold Time, Clock to Data (Figure 3) t rec Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure ) Minimum Pulse Width, Set or Reset (Figure 2) t r, t f Maximum Input Rise and Fall Times (Figures, 2, 3) ORDERING INFORMATION Device Package Shipping 4HC4D 4HC4DG 4HC4DR2 4HC4DR2G 4HC4DTR2 4HC4DTR2G SOIC 4 SOIC 4 (Pb Free) SOIC 4 SOIC 4 (Pb Free) TSSOP 4* TSSOP 4* 55 Units / Rail 2 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 4
5 SWITCHING WAEFORMS 90% 0% t f t r /f max SET OR RESET Q OR Q Q or Q 90% 0% t PLH t TLH t THL Q OR Q t PLH t rec Figure. Figure 2. DATA t su ALID t h DEICE UNDER TEST OUTPUT TEST POINT C L * *Includes all probe and jig capacitance Figure 3. Figure 4. 4, 0 SET DATA 2, 2 5, 9 Q 3, 6, 8 Q, 3 RESET Figure 5. EXPANDED LOGIC DIAGRAM 5
6 PACKAGE DIMENSIONS SOIC 4 CASE A 03 ISSUE H T SEATING PLANE A 4 8 G B P PL 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES C R X 45 F DIM MIN MAX MIN MAX A B C D D 4 PL K M J F G.2 BSC BSC 0.25 (0.00) M T B S A S J K M 0 0 P R SOLDERING FOOTPRINT* 4X 0.58 X.04 4X.52.2 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
7 PACKAGE DIMENSIONS TSSOP 4 CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S S N (0.00) M B U A G H N J J F DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 4X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL Compatible Inputs The is a single gate CMOS Schmitt trigger inverter fabricated with silicon gate CMOS technology. It achieves high speed operation
MC74AC259, MC74ACT Bit Addressable Latch
8-Bit Addressable Latch The MC259/T259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing single
MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter
February 1984 Revised February 1999 MM74HC4020 MM74HC4040 14-Stage Binary Counter 12-Stage Binary Counter General Description The MM74HC4020, MM74HC4040, are high speed binary ripple carry counters. These
74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
74LCX841 Low oltage 10-Bit Traparent Latch with 5 Tolerant Inputs and Outputs General Description The LCX841 coists of ten latches with 3-STATE outputs for bus organized system applicatio. The device is
MC14099B. 8-Bit Addressable Latches
-Bit Addressable Latches The MC99B is an bit addressable latch. Data is entered in serial form when the appropriate latch is addressed (via address pi A, A, A) and write disable is in the low state. For
MC74VHC1G125. Noninverting 3 State Buffer
MC74CG2 Noninverting 3 State Buffer The MC74CG2 is an advanced high speed CMOS noninverting 3 state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
KK74HC221A. Dual Monostable Multivibrator TECHNICAL DATA PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE
TECNICAL DATA KK74C22A Dual Monostable Multivibrator The KK74C22A is identical in pinout to the LS/ALS22. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible
74VHC393 Dual 4-Bit Binary Counter
Dual 4-Bit Binary Counter General Description March 1993 Revised March 1999 The HC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
MC74HC86A. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate High Performance Silicon Gate CMOS The MC4HC86A is identical in pinout to the S86. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
74FST Bit, 4 Port Bus Exchange Switch
4 Bit, 4 Port Bus Exchange Switch The ON Semiconductor 74FST3400 is a 4 bit, 4 port bus exchange switch. The device is CMOS TTL compatible when operating between 4.0 and 5.5 Volts. The device exhibits
8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT RESISTER High-Performance Silicon-Gate CMOS
TECNICAL DATA 8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SIFT RESISTER igh-performance Silicon-ate CMOS The may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The is
MC74ACT Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The MC74ACT323 is an 8-bit universal shift/storage register with3-state outputs. Its function is similar to the MC74ACT299
Octal 3-State Noninverting D Flip-Flop
TEHNIAL ATA IN74H74A Octal 3-State Noninverting Flip-Flop High-Performance Silicon-Gate MOS N SUFFIX PLASTI IP The IN74H74A is identical in pinout to the LS/ALS74. The device inputs are compatible with
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163. Synchronous Presettable Binary Counter
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high speed synchronous modulo 16 binary counters. They are synchronously
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC74AC32, MC74ACT32 Quad 2 Input NAND Schmitt Trigger The MC74AC/74ACT32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free
74VHC273 Octal D-Type Flip-Flop
74VHC273 Octal D-Type Flip-Flop General Description The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar
BAS19LT1, BAS20LT1, BAS21LT1, BAS21DW5T1. High Voltage Switching Diode HIGH VOLTAGE SWITCHING DIODE. Pb Free Packages are Available.
BAS9LT, BAS0LT, BASLT, BASDWT Preferred Devices High Voltage Switching Diode Features PbFree Packages are Available MAXIMUM RATINGS Continuous Reverse Voltage Rating Symbol Value Unit BAS9 BAS0 BAS Repetitive
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
MC74HC4040A. 12 Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74HA 2 Stage Binary Ripple ounter High Performance Silicon Gate MOS The M74A is identical in pinout to the standard MOS M. The device inputs are compatible with standard MOS outputs; with pullup resistors,
MM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption