MC10EP131, MC100EP V / 5VНECL Quad D Flip Flop with Set, Reset, and Differential Clock
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1 3.3V / 5VНECL Quad D Flip Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master slaved D flip flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available. Each flip flop may be clocked separately by holding Common Clock (C C ) LOW and C C HIGH, then using the differential Clock Enable inputs for clocking (C 0 3, C 0 3 ). Common clocking is achieved by holding the differential inputs C 0 3 LOW and C 0 3 HIGH while using the differential Common Clock (C C ) to clock all four flip flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state. Individual asynchronous resets (R 0 3 ) and an asynchronous set (SET) are provided. Data enters the master when both C C and C 0 3 are LOW, and transfers to the slave when either C C or C 0 3 (or both) go HIGH. The 100 Series contains temperature compensation. Features 460 ps Typical Propagation Delay Maximum Frequency > 3 GHz Typical Differential Individual and Common Clocks Individual Asynchronous Resets Asynchronous Set PECL Mode Operating Range: V CC = 3.0 V to 5.5 V with V EE = 0 V NECL Mode Operating Range: V CC = 0 V with V EE = 3.0 V to 5.5 V Open Input Default State Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at V EE Pb Free Packages are Available FA SUFFIX CASE 873A 1 32 QFN32 MN SUFFIX CASE 488AM MARKING DIAGRAM* MCxxx EP131 AWLYYWWG MCxxx EP131 AWLYYWW xxx = 10 or 100 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. 1 Semiconductor Components Industries, LLC, Publication Order Number: MC10EP131/D
2 Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Characteristics Human Body Model Machine Model Charged Device Model Value 75 k N/A > 2 kv > 100 V > 2 kv Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb Free Pkg Level 2 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V in Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. 935 Devices Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V CC PECL Mode Power Supply V EE = 0 V 6 V V EE NECL Mode Power Supply V CC = 0 V 6 V V I PECL Mode Input Voltage NECL Mode Input Voltage V EE = 0 V V CC = 0 V I out Output Current Continuous Surge V I V CC 6 V I V EE 6 I BB V BB Sink/Source ± 0.5 ma T A Operating Temperature Range 40 to +85 C T stg Storage Temperature Range 65 to +150 C JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP JC Thermal Resistance (Junction to Case) Standard Board 32 LQFP 12 to 17 JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm JC Thermal Resistance (Junction to Case) 2S2P 12 T sol Wave Solder Pb Pb Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability V V ma ma C 3
3 Table 7. 10EP DC CHARACTERISTICS, NECL V CC = 0 V, V EE = 5.5 V to 3.0 V (Note 8) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 9) mv V OL Output LOW Voltage (Note 9) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 10) V EE V EE V EE V 8. Input and output parameters vary 1:1 with V CC. 9. All loading with 50 to V CC 2.0 V. 10. min varies 1:1 with V EE, max varies 1:1 with V CC. The range is referenced to the most positive side of the differential Table EP DC CHARACTERISTICS, PECL V CC = 3.3 V, V EE = 0 V (Note 11) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 12) mv V OL Output LOW Voltage (Note 12) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 13) V 11. Input and output parameters vary 1:1 with V CC. V EE can vary +0.3 V to 2.2 V. 12.All loading with 50 to V CC 2.0 V. 13. min varies 1:1 with V EE, max varies 1:1 with V CC. The range is referenced to the most positive side of the differential 5
4 Table EP DC CHARACTERISTICS, PECL V CC = 5.0 V, V EE = 0 V (Note 14) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 15) mv V OL Output LOW Voltage (Note 15) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 16) V 14.Input and output parameters vary 1:1 with V CC. V EE can vary +2.0 V to 0.5 V. 15.All loading with 50 to V CC 2.0 V. 16. min varies 1:1 with V EE, max varies 1:1 with V CC. The range is referenced to the most positive side of the differential Table EP DC CHARACTERISTICS, NECL V CC = 0 V, V EE = 5.5 V to 3.0 V (Note 17) I EE Power Supply Current ma V OH Output HIGH Voltage (Note 18) mv V OL Output LOW Voltage (Note 18) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv (Note 19) V EE V EE V EE V 17.Input and output parameters vary 1:1 with V CC. 18.All loading with 50 to V CC 2.0 V. 19. min varies 1:1 with V EE, max varies 1:1 with V CC. The range is referenced to the most positive side of the differential 6
5 Table 11. AC CHARACTERISTICS V CC = 0 V; V EE = 3.0 V to 5.5 V or V CC = 3.0 V to 5.5 V; V EE = 0 V (Note 20) f max Maximum Frequency (See Figure 4. Frequency vs. V OUTpp and JITTER) t PLH, Propagation Delay to C 0 3 t PHL Output Differential C C R 0 3 SET > 3 > 3 > 3 GHz t RR Set/R0 3 Recovery ps t S t H Setup Time Hold Time ps t PW Minimum Pulse Rate SET, R ps t JITTER Cycle to Cycle Jitter (See Figure 4. Frequency vs. V OUTpp and JITTER) t r Output Rise/Fall Times Q, Q t f (20% 80%) 0.2 < < < 1 ps ps 20.Measured using a 750 mv source, 50% duty cycle clock source. All loading with 50 to V CC 2.0 V. 7
6 ORDERING INFORMATION Device Package Shipping MC10EP131FA 250 Units / Tray MC10EP131FAG 250 Units / Tray MC10EP131FAR / Tape & Reel MC10EP131FAR2G 2000 / Tape & Reel MC100EP131FA 250 Units / Tray MC100EP131FAG 250 Units / Tray MC100EP131FAR / Tape & Reel MC100EP131FAR2G 2000 / Tape & Reel MC10EP131MNG MC10EP131MNR4G MC100EP131MNG MC100EP131MNR4G 74 Units / Tray 1000 / Tape & Reel 74 Units / Tray 1000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D ECL Clock Distribution Techniques AN1406/D Designing with PECL (ECL at +5.0 V) AN1503/D ECLinPS I/O SPiCE Modeling Kit AN1504/D Metastability and the ECLinPS Family AN1568/D Interfacing Between LVDS and ECL AN1672/D The ECL Translator Guide AND8001/D Odd Number Counters Design AND8002/D Marking and Date Codes AND8020/D Termination of ECL Logic Devices AND8066/D Interfacing with ECLinPS AND8090/D AC Characteristics of ECL Devices 9
7 PACKAGE DIMENSIONS A1 32 A 25 4X 32 LEAD LQFP CASE 873A 02 ISSUE C 0.20 (0.008) AB T U Z T, U, Z T 1 U P AE B 9 SEATING PLANE B1 AB AC 8 9 S1 DETAIL Y Z S G 0.10 (0.004) AC 17 4X V1 V 0.20 (0.008) AC T U Z DETAIL AD C E 8X M DETAIL Y AE R BASE METAL N FÉÉ ÉÉ J D 0.20 (0.008) M AC T U Z SECTION AE AE H W DETAIL AD X K Q GAUGE PLANE (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A BSC BSC A BSC BSC B BSC BSC B BSC BSC C D E F G BSC BSC H J K M 12 REF 12 REF N P BSC BSC Q R S BSC BSC S BSC BSC V BSC BSC V BSC BSC W REF REF X REF REF 10
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MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where
MC74HC244A. Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver. High Performance Silicon Gate CMOS
Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL Compatible Inputs The is a single gate CMOS Schmitt trigger inverter fabricated with silicon gate CMOS technology. It achieves high speed operation
MC1403, B. Low Voltage Reference PRECISION LOW VOLTAGE REFERENCE
Low Voltage Reference A precision bandgap voltage reference designed for critical instrumentation and D/A converter applications. This unit is designed to work with D/A converters, up to bits in accuracy,
74F161A 74F163A Synchronous Presettable Binary Counter
74F161A 74F163A Synchronous Presettable Binary Counter General Description Ordering Code: The F161A and F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for
MC74VHC1G125. Noninverting 3 State Buffer
MC74CG2 Noninverting 3 State Buffer The MC74CG2 is an advanced high speed CMOS noninverting 3 state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
74FR74 74FR1074 Dual D-Type Flip-Flop
74FR74 74FR1074 Dual D-Type Flip-Flop General Description The 74FR74 and 74FR1074 are dual D-type flip-flops with true and complement (Q/Q) outputs. On the 74FR74, data at the D inputs is traferred to
SN74LS157MEL. Quad 2 Input Multiplexer LOW POWER SCHOTTKY
Quad 2 Input Multiplexer The LSTTL/ MSI is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs
with LSTTL Compatible Inputs
with LSTTL Compatible Inputs The MCLVX9 is an 8 bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides
MC10E131, MC100E131. 5VНECL 4-Bit D Flip-Flop
5VНECL 4-Bit Flip-Flop escription The MC10E/100E131 is a quad master-slave -type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (C C ) LOW and using
ORDERING INFORMATION T A PACKAGE ORDERABLE PARTNUMBER. SOIC - D -40 to 85 SOP NS Reel of 2000 MC74HC164NSR HC164
Wide Operating Voltage Range of 2 V to 6V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80- A Max I CC Typical t pd =20 ns 4-mA Output Drive at 5V Low Input Current of 1 A Max AND-Gated
V N (8) V N (7) V N (6) GND (5)
4-Channel Low Capacitance Dual-Voltage ESD Protection Array Features Three Channels of Low Voltage ESD Protection One Channel of High Voltage ESD Protection Provides ESD Protection to IEC61000 4 2 Level
NCS1002A. Constant Voltage / Constant Current Secondary Side Controller
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INT RST TEMP RANGE PIN- PACKAGE TOP MARK PKG CODE PART. -40 C to +125 C -40 C to +125 C 16 QSOP E16-4 MAX7323AEE+ 16 TQFN-EP* 3mm x 3mm MAX7323ATE+
19-3806; Rev 1; 7/07 INT RST Ω μ PART MAX7323AEE+ MAX7323ATE+ * TEMP RANGE -40 C to +125 C -40 C to +125 C PIN- PACKAGE TOP MARK PKG CODE 16 QSOP E16-4 16 TQFN-EP* 3mm x 3mm ADE T1633-4 PART INPUTS INTERRUPT
Battery Monitors Notebooks and PDA s General Purpose Portable Devices General Purpose Low Voltage Applications +V CC.
LMV33, NCV33, LMV393, LMV339 Single, Dual, Quad General Purpose, Low Voltage Comparators The LMV33 is a CMOS single channel, general purpose, low voltage comparator. The LMV393 and LMV339 are dual and
NB3L553/D. 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer
2.5 V / 3.3 V / 5.0 V :4 Clock Fanout Buffer Description The is a low skew to 4 clock fanout buffer, designed for clock distribution in mind. The specifically guarantees low output to output skew. Optimal
74F269 8-Bit Bidirectional Binary Counter
74F269 8-Bit Bidirectional Binary Counter General Description The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry lookahead for easy
Presettable Counters High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC1A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HC1A is identical in pinout to the LS/ALS1. The device inputs are compatible with standard CMOS outputs; with pullup
Low Voltage 2-1 Mux, Level Translator ADG3232
Low Voltage 2-1 Mux, Level Translator ADG3232 FEATURES Operates from 1.65 V to 3.6 V Supply Rails Unidirectional Signal Path, Bidirectional Level Translation Tiny 8-Lead SOT-23 Package Short Circuit Protection
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MMBZ5xxBLT Series, SZMMBZ5xxBLTG Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
FIN1531 5V LVDS 4-Bit High Speed Differential Driver
FIN1531 5V LVDS 4-Bit High Speed Differential Driver General Description This quad driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.
Data Sheet FN3118.4 SPST 4-Channel Analog Switch The is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation,
SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY
Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops
DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or