MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
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1 MC32, MC32 Quad 2 Input NAND Schmitt Trigger The MC/32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free output signals. In addition, they have greater noise margin than conventional NAND gates. Each circuit contains a 2 input Schmitt trigger. The Schmitt trigger uses positive feedback to effectively speed up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive going and negative going input threshold is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations. Features Schmitt Trigger Inputs Outputs Source/Sink 24 ma ACT32 Has TTL Compatible Inputs Pb Free Packages are Available PDIP 4 N SUFFIX CASE 646 D SUFFIX CASE 75A SOEIAJ 4 M SUFFIX CASE ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet GND Figure. Pinout; 4 Lead Packages Conductors (Top iew) FUNCTION TABLE Inputs Output A B Y L L H L H H H L H H H L H = HIGH oltage Level L = LOW oltage Level Semiconductor Components Industries, LLC, 2006 Publication Order Number: MC32/D
2 MC32, MC32 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Supply oltage AC ACT in, out DC Input oltage, Output oltage (Ref. to GND) 0 t r, t f Input Rise and Fall Time (Note ) AC Devices except Schmitt Inputs t r, t f Input Rise and Fall Time (Note 2) ACT Devices except Schmitt T J Junction Temperature (PDIP) 40 C T A Operating Ambient Temperature Range C I OH Output Current High 24 ma I OL Output Current Low 24 ma. in from 30% to 70% ; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. in from 0.8 to 2.0 ; see individual Data Sheets for devices that differ from the typical input rise and fall times. ns/ DC CHARACTERISTICS Symbol Parameter OH Minimum High Level Output oltage Typ T A = 40 C to +85 C Guaranteed Limits Conditions I OUT = 50 A OL Maximum Low Level Output oltage * IN = IL or IH ma I OH 24 ma ma I OUT = 50 A I IN Maximum Input Leakage Current * IN = IL or IH ma I OL 24 ma ma 5.5 ±0. ±.0 A I =, GND I OLD Minimum Dynamic ma OLD =.65 Max I OHD Output Current ma OHD = 3.85 Min I CC Maximum Quiescent Supply Current A IN = or GND *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: I IN and I 3.0 are guaranteed to be less than or equal to the respective
3 MC32, MC32 AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL38/D) Symbol t PLH t PHL Propagation Delay Propagation Delay *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. Parameter * T A = 40 C to +85 C Min Typ Max Min Max ns ns Fig. No DC CHARACTERISTICS Symbol Parameter T A = 40 C to +85 C Conditions Typ Guaranteed Limits OH Minimum High Level Output oltage I OUT = 50 A OL Maximum Low Level Output oltage * IN = IL or IH ma I OH 24 ma I OUT = 50 A I IN Maximum Input Leakage Current * IN = IL or IH ma I OL 24 ma 5.5 ±0. ±.0 A I =, GND I CCT Additional Max. I CC /Input ma I = 2. I OLD Minimum Dynamic ma OLD =.65 Max I OHD Output Current ma OHD = 3.85 Min I CC Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time A IN = or GND AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL38/D) Symbol Parameter * T A = 40 C to +85 C Min Typ Max Min Max t PLH Propagation Delay ns 3 6 t PHL Propagation Delay ns 3 5 *oltage Range 5.0 is 5.0 ±0.5. Fig. No. 3
4 MC32, MC32 INPUT CHARACTERISTICS (unless otherwise specified) Symbol Parameter Test Conditions Maximum Positive t T Threshold A = Worst Case Minimum Negative t T Threshold A = Worst Case h(max) Maximum Hysteresis T A = Worst Case h(min) Minimum Hysteresis T A = Worst Case CAPACITANCE Symbol Parameter alue Typ Test Conditions C IN Input Capacitance 4.5 pf = 5.0 C PD Power Dissipation Capacitance 30 pf = 5.0 4
5 MC32, MC32 MARKING DIAGRAMS 4 PDIP 4 MC32N AWLYYWWG 4 AC32G AWLYWW 4 SOEIAJ 4 32 ALYWG 4 MC32N AWLYYWWG 4 ACT32G AWLYWW 4 32 ALYWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb Free Package ORDERING INFORMATION Device Package Shipping MC32N MC32NG MC32N MC32NG MC32D MC32DG MC32DR2 MC32DR2G MC32D MC32DG MC32DR2 MC32DR2G MC32MEL MC32MELG MC32MEL MC32MELG PDIP 4 PDIP 4 PDIP 4 PDIP 4 SOEIAJ 4 SOEIAJ 4 SOEIAJ 4 SOEIAJ 4 25 s/rail 55 s/rail 2500/Tape & Reel 55 s/rail 2500/Tape & Reel 2000/Tape & Reel 5
6 MC32, MC32 PACKAGE DIMENSIONS CASE 75A 03 ISSUE H T SEATING PLANE A 4 8 G 7 B P 7 PL 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES C R X 45 F DIM MIN MAX MIN MAX A B C D D 4 PL K M J F G.27 BSC BSC 0.25 (0.00) M T B S A S J K M P R SOLDERING FOOTPRINT* 4X X X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7
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Features Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
MM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
MC74VHC1G125. Noninverting 3 State Buffer
MC74CG2 Noninverting 3 State Buffer The MC74CG2 is an advanced high speed CMOS noninverting 3 state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
MM74HC244 Octal 3-STATE Buffer
MM74HC244 Octal 3-STATE Buffer General Description The MM74HC244 is a non-inverting buffer and has two active low enables (1G and 2G); each enable independently controls 4 buffers. This device does not
MC74AC377, MC74ACT377. Octal D Flip Flop with Clock Enable
Octal FlipFlop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, -type flip-flops with individual inputs and outputs. The common buffered Clock () input loads all flip-flops simultaneously,
MC74HC138A. 1 of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demuliplexer High Performance Silicon Gae CMOS The is idenical in pinou o he LS8. The device inpus are compaible wih sandard CMOS oupus; wih pullup resisors, hey are compaible wih LSTTL oupus.
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power