MC14521B. 24 Stage Frequency Divider
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- Melinda Peters
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1 24Stage Frequency Divider The coists of a chain of 24 flipflops with an input circuit that allows three modes of operation. The input will function as a crystal oscillator, an C oscillator, or as an input buffer for an external oscillator. Each flipflop divides the frequency of the previous flipflop by two, coequently this part will count up to 2 24 = 6,777,26. The count advances on the negative going edge of the clock. The outputs of the last sevetages are available for added flexibility. Features All Stages are esettable eset Disables the C Oscillator for Low Standby Power Drain C and Crystal Oscillator Outputs Are Capable of Driving External Loads Test Mode to educe Test Time and Pi Brought Out on Crystal Oscillator Inverter to Allow the Connection of External esistors for LowPower Operation Supply Voltage ange = 3. to 8 Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load over the ated Temperature ange PbFree Packages are Available* MAXIMUM ATINGS (Voltages eferenced to ) Parameter Symbol Value Unit PDIP6 P SUFFIX CASE SOIC6 D SUFFIX CASE 75B SOEIAJ6 F SUFFIX CASE MAKING DIAGAMS CP AWLYYWWG 452BG AWLYWW ALYWG DC Supply Voltage ange.5 to +8. V Input or Output Voltage ange (DC or Traient) Input or Output Current (DC or Traient) per Pin V in, V out.5 to +.5 V I in, I out ± ma A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = PbFree Package Power Dissipation, per Package (Note ) P D 5 mw Ambient Temperature ange T A 55 to +25 C Storage Temperature ange T stg 65 to +5 C Lead Temperature (8Second Soldering) T L 26 C Stresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating Conditio is not implied. Extended exposure to stresses above the ecommended Operating Conditio may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: 7. mw/ C From 65 C To 25 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. ODEING INFOMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D.
2 BLOCK DIAGAM ESET 2 IN 6 STAGES THU 7 STAGES 8 THU 24 Q8 Q Q2 PIN ASSIGNMENT 6 7 OUT OUT2 = PIN 6 = PIN ESET Q2 Q Q8 Output Count Capacity Q8 2 8 = 262,44 Q 2 = 524, =,48,576 Q2 2 2 = 2,7, = 4,4, = 8,388, = 6,777,26 8 IN ODEING INFOMATION CP CPG Device Package Shipping PDIP6 PDIP6 25 Units / ail D DG D2 D2G F FG SOIC6 SOIC6 SOIC6 SOIC6 SOEIAJ6 SOEIAJ6 48 Units / ail 25 / Tape & eel 5 Units / ail FEL FELG SOEIAJ6 SOEIAJ6 2 / Tape & eel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specificatio Brochure, BD8/D. 2
3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTICAL CHAACTEISTICS (Voltages eferenced to ) Characteristic Output Voltage V in = or V in = or Level Level Input Voltage Level (V O = 4.5 or.5 ) (V O =. or. ) (V O = or.5 ) Level (V O =.5 or 4.5 ) (V O =. or. ) (V O =.5 or ) Output Drive Current (V OH = 2.5 ) Source (V OH = 4.6 ) Pi 4 & 7 (V OH =.5 ) (V OH = ) (V OH = 2.5 ) Source (V OH = 4.6 ) Pi,, (V OH =.5 ), 2, 3, 4 (V OH = ) and 5 (V OL =.4 ) Sink (V OL =.5 ) (V OL =.5 ) Symbol V OL 5 V OH 5 V IL 5 V IH 5 I OH 5 5 I OL 5 55 C 25 C 25 C Min Max Min Typ (Note 2) Max Min Max Input Current I in 5 ±. ±. ±. ±. Adc Unit madc madc madc Input Capacitance (V in = ) C in 7.5 pf Quiescent Current (Per Package) Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) ( = 5 pf on all outputs, all buffers switching) I DD 5 I T I T = (.42 A/kHz) f + I DD I T = (.85 A/kHz) f + I DD I T = (.4 A/kHz) f + I DD 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at 25 C. 4. To calculate total supply current at loads other than 5 pf: I T ( ) = I T (5 pf) + ( 5) Vfk where: I T is in A (per package), in pf, V = ( ) in volts, f in khz is input frequency, and k = Adc Adc 3
4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHAACTEISTICS (Note 5) ( = 5 pf, T A = 25 C) Characteristic Output ise and Fall Time (Counter Outputs) t TLH, t THL = (.5 /pf) + 25 t TLH, t THL = (.75 /pf) t TLH, t THL = (.55 /pf) Propagation Delay Time Clock to Q8 t PHL, t PLH = (.7 /pf) t PHL, t PLH = (.66 /pf) t PHL, t PLH = (.5 /pf) Clock to t PHL, t PLH = (.7 /pf) + 55 t PHL, t PLH = (.66 /pf) t PHL, t PLH = (.5 /pf) Propagation Delay Time eset to Q n t PHL = (.7 /pf) + 25 t PHL = (.66 /pf) t PHL = (.5 /pf) + 35 Symbol t TLH, t THL 5 t PHL, t PLH t PHL Clock Pulse Width t WH(cl) 5 Clock Pulse Frequency f cl 5 Clock ise and Fall Time t TLH, t THL 5 eset Pulse Width t WH() 5 eset emoval Time t rem Min Typ (Note 6) Max Unit The formulas given are for the typical characteristics only at 25 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance s MHz s 5 F I D. F CEAMIC PULSE GENEATO Q8 Q Q2 V in 2 2 % 5% % V 5% DUTY CYCLE Figure. Power Dissipation Test Circuit and Waveform 4
5 PULSE GENEATO Q8 Q Q2 Q n % % % t WL t WH 5% % % t PLH t PHL t TLH t THL Figure 2. Switching Time Test Circuit and Waveforms C S o C T 8 M IN * OUT Q8 Q Q2 *Optional for low power operation, k 7 k. Figure 3. Crystal Oscillator Circuit * Characteristic 5 khz Circuit Crystal Characteristics esonant Frequency 5 Equivalent esistance, S. External esistor/capacitor Values o C T C S Frequency Stability Frequency Change as a Function of (T A = 25 C) Change from V to V Change from V to 5 V Frequency Change as a Function of Temperature ( = V) T A Change from 55 C to + 25 C MC452 only Complete Oscillator* T A Change from +25 C to+25 C MC452 only Complete Oscillator* khz Circuit Unit khz k k pf pf *Complete oscillator includes crystal, capacitors, and resistors. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure 4. Typical Data for Crystal Oscillator Circuit 5
6 FEQUENCY DEVIATION (%) = 5 V V V Figure 5. C Oscillator Stability TEST CICUIT FIGUE 7 2 TC = 56 k, S =, f =.5 = V, T A = 25 C { C = pf 6 S = 2 k, f = 7.8 = V, T A = 25 C T A, AMBIENT TEMPEATUE ( C), DEVICE ONLY f, OSCILLATO FEQUENCY (khz) f AS A FUNCTION OF C ( TC = 56 k ) ( S = 2 k) = V TEST CICUIT FIGUE 7 f AS A FUNCTION OF TC (C = pf) ( S 2 TC ).. k k k. m TC, ESISTANCE (OHMS).... C, CAPACITANCE ( F) Figure 6. C Oscillator Frequency as a Function of TC and C S TC C IN OUT Q8 Q Q2 PULSE GENEATO IN Q8 Q Q2 OUT Figure 7. C Oscillator Circuit Figure 8. Functional Test Circuit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ FUNCTIONAL TEST SEQUENCE A test function (see Figure 8) has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8stage sectio, and 255 counts are loaded in each of the 8stage sectio in parallel. All flipflops are now at a logic. The counter is now returned to the normal 24stages in series configuration. One more pulse is entered into Input 2 (In 2) which will cause the counter to ripple from an all state to an all state. Inputs Outputs Comments eset In 2 Out 2 Q8 thru GND Counter is in three 8stage sectio in parallel mode Counter is reset. In 2 and Out 2 are connected together. First to traition on In 2, Out 2 node. 255 to traitio are clocked into this In 2, Out 2 node. The 255th to traition. GND Counter converted back to 24stages in series mode. Out 2 converts back to an output. Counter ripples from an all state to an all stage. 6
7 LOGIC DIAGAM 5 ESET 2 IN 2 STAGES 8 3 THU 7 7 OUT STAGES 6 THU Q8 Q 2 3 Q2 4 5 = PIN 6 = PIN 8 7
8 PACKAGE DIMENSIONS PDIP6 CASE 6488 ISSUE T A 6 8 B NOTES:. DIMENSIONING AND TOLEANCING PE ANSI Y4.5M, CONTOLLING DIMENSION: INCH. 3. DIMENSION L TO CENTE OF LEADS WHEN FOMED PAALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. OUNDED CONES OPTIONAL. H G F D 6 PL S C K.25 (.) M T T SEATING PLANE A M J L M INCHES MILLIMETES DIM MIN MAX MIN MAX A B C D F G. BSC 2.54 BSC H BSC.27 BSC J K L M S SOIC6 CASE 75B5 ISSUE J A 6 8 B P 8 PL.25 (.) M B S NOTES:. DIMENSIONING AND TOLEANCING PE ANSI Y4.5M, CONTOLLING DIMENSION: MILLIMETE. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD POTUSION. 4. MAXIMUM MOLD POTUSION.5 (.6) PE SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATEIAL CONDITION. T SEATING PLANE G K C D 6 PL.25 (.) M T B S A S M X 45 J F MILLIMETES INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M 7 7 P
9 PACKAGE DIMENSIONS SOEIAJ6 CASE 66 ISSUE A e 6 Z b D A H E A.3 (.5) M. (.4) 8 E VIEW P M L E Q L DETAIL P c NOTES: М. DIMENSIONING AND TOLEANCING PE ANSI Y4.5M, 82. М 2. CONTOLLING DIMENSION: MILLIMETE. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH O POTUSIONS AND AE MEASUED AT THE PATING LINE. MOLD FLASH O POTUSIONS SHALL NOT EXCEED.5 (.6) PE SIDE. М 4. TEMINAL NUMBES AE SHOWN FO EFEENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATEIAL CONDITION. DAMBA CANNOT BE LOCATED ON THE LOWE ADIUS O THE FOOT. MINIMUM SPACE BETWEEN POTUSIONS AND ADJACENT LEAD TO BE.46 (.8). MILLIMETES INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z
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TECNICAL DATA IN74C33A Octal 3-State Inverting Traparent Latch igh-performance Silicon-ate CMOS The IN74C33A is identical in pinout to the LS/ALS33. The device inputs are compatible with standard CMOS
Excellent Integrated System Limited
Excellent Integrated System Limited Stocking Distributor Click to view price, real time Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor CD4050BCN For any questio, you can email us
MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS
MC74C00A Quad 2 Input NAND Gate igh Performance Silicon Gate CMOS The MC74C00A is identical in pinout to the S00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they
MC14040B. 12-Bit Binary Counter
M4040B 2Bi Binary ouner The M4040B 2sage binary couner is coruced wih MOS Phannel and Nhannel enhancemen mode devices in a single monolihic srucure. This par is designed wih an inpu wave shaping circui
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
MC1403, B. Low Voltage Reference PRECISION LOW VOLTAGE REFERENCE
Low Voltage Reference A precision bandgap voltage reference designed for critical instrumentation and D/A converter applications. This unit is designed to work with D/A converters, up to bits in accuracy,
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
Hex 3-State Noninverting Buffer with Common Enables High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C365A ex 3-State Noninverting Buffer with Common Enables igh-performance Silicon-ate CMOS The IN74C365A is identical in pinout to the LS/ALS365. The device inputs are compatible with
CD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high
CD4021BC 8-Stage Static Shift Register
8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C244A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver igh-performance Silicon-ate CMOS The IN74C244A is identical in pinout to the LS/ALS244. The device inputs are compatible
74F193 Up/Down Binary Counter with Separate Up/Down Clocks
April 1988 Revised September 2000 Up/Down Binary Counter with Separate Up/Down Clocks General Description The is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
Dual 4-Input Data Selector/Multiplexer High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C153A Dual 4-Input Data Selector/Multiplexer igh-performance Silicon-ate CMOS The IN74C153A is identical in pinout to the LS/ALS153. The device inputs are compatible with standard CMOS
Quad 2-Input NAND Gate with Open-Drain Outputs High-Performance Silicon-Gate CMOS
IN74C3A Quad 2-Input NAND ate with Open-Drain Outputs igh-performance Silicon-ate CMOS The IN74C3A is identical in pinout to the LS/ALS3. The device inputs are compatible with standard CMOS outputs; with
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS
Quad 2 Input NAND Gate with Schmitt Trigger Inputs High Performance Silicon Gate CMOS The is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
MC14516B. Binary Up/Down Counter
M456B Binary Up/Down ounter The M456B synchronous up/down binary counter is cotructed with MOS Pchannel and Nchannel enhancement mode devices in a monolithic structure. This counter can be preset by applying
8-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C251A 8-Input Data Selector/Multiplexer with 3-State Outputs igh-performance Silicon-ate CMOS The IN74C251A is identical in pinout to the LS/ALS251. The device inputs are compatible with
2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
74F Bit D-Type Flip-Flop
74F821 10-Bit D-Type Flip-Flop General Description The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout. Ordering Code: Features 3-STATE Outputs Devices also
CD4049UBC CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer
CD4049UBC CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer General Description The CD4049UBC and CD4050BC hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with
CD74HC221, CD74HCT221
November 997 SEMIONDUTO D74H22, D74HT22 High Speed MOS Logic Dual Monostable Multivibrator with eset Features Description Overriding ESET Terminates Output Pulse Triggering from the Leading or Trailing
CD4528BC Dual Monostable Multivibrator
Dual Monostable Multivibrator General Description The CD4528BC is a dual monostable multivibrator. Each device is retriggerable and resettable. Triggering can occur from either the rising or falling edge
MC14543B. BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals
M4543B BD-to-Seven Segment Latch/Decoder/Driver for Liquid rystals The M4543B BDtoseven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is cotructed with complementary
MM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
MM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
MM74HC244 Octal 3-STATE Buffer
MM74HC244 Octal 3-STATE Buffer General Description The MM74HC244 is a non-inverting buffer and has two active low enables (1G and 2G); each enable independently controls 4 buffers. This device does not
NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register
NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs
SN74LS145MEL. 1 of 10 Decoder/Driver Open Collector LOW POWER SCHOTTKY
of 0 Decoder/Driver Open Collector The SN74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain off for