Presettable Counters High-Performance Silicon-Gate CMOS

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Junior Woods
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1 TECHNICAL DATA IN74HC1A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HC1A is identical in pinout to the LS/ALS1. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC1A is programmable 4-bit synchronous counter that feature parallel Load, asynchronous Reset, a Carry Output for cascading and count-enable controls. The IN74HC1A is binary counter with asynchronous Reset. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: to V Low Input Current: 1.0 µa High Noise Immunity Characteristic of CMOS Devices LOGIC DIAGRAM ORDERING INFORMATION IN74HC1AN Plastic IN74HC1AD SOIC T A = -55 to 1 C for all packages PIN ASSIGNMENT PIN =V CC PIN 8 = GND FUNCTION TABLE Inputs Reset Load Enable P Enable T Outputs Clock Q0 Q1 Q2 Q Function L X X X X L L L L Reset to 0 H L X X P0 P1 P2 P Preset Data H H X L No change No count H H L X No change No count H H H H Count up Count H X X X No change No count X=don t care P0,P1,P2,P = logic level of Data inputs Ripple Carry Out = Enable T Q0 Q1 Q2 Q

2 MAXIMUM RATINGS * Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V V IN DC Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V V OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 V I IN DC Input Current, per Pin ± ma I OUT DC Output Current, per Pin ± ma I CC DC Supply Current, V CC and GND Pi ±50 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to +0 C T L Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 10 mw/ C from 65 to 1 C SOIC Package: : - 7 mw/ C from 65 to 1 C mw 260 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC DC Supply Voltage (Referenced to GND) V V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) V CC = V V CC = V V CC = V This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be cotrained to the range GND (V IN or V OUT ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.

3 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditio V C to -55 C V IH Minimum High- Level Input Voltage V IL Maximum Low - Level Input Voltage V OH Minimum High- Level Output Voltage V OUT = V or V CC - V I OUT µa V OUT = V or V CC - V I OUT µa V IN =V IH or V IL I OUT µa V CC Guaranteed Limit C C Unit V V V V IN =V IH or V IL I OUT ma I OUT 7.8 ma V OL Maximum Low- Level Output Voltage V IN =V IH or V IL I OUT µa V I IN I CC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) V IN =V IH or V IL I OUT ma I OUT 7.8 ma V IN =V CC or GND ± ±1.0 ±1.0 µa V IN =V CC or GND I OUT =0µA µa

4 AC ELECTRICAL CHARACTERISTICS (C L =50pF,Input t r =t f = ) V CC Symbol Parameter V C to -55 C f max Maximum Clock Frequency (Figures 1,6) t PLH Maximum Propagation Delay Clock to Q t PHL (Figures 1,6) t PHL t PLH Maximum Propagation Delay Reset to Q (Figures 2 and 6) Maximum Propagation Delay Enable T to Ripple Carry Out t PHL (Figures,6) t PLH Maximum Propagation Delay Clock to Ripple t PHL Carry Out (Figures 1,6) t PHL t TLH, t THL Maximum Propagation Delay Reset to Ripple Carry Out (Figures 2,6) Maximum Output Traition Time, Any Output (Figures 1 and 6) Guaranteed Limit 85 C 1 C Unit C IN Maximum Input Capacitance pf MHz C PD Power Dissipation Capacitance (Per Gate) Used to determine the no-load dynamic power coumption: P D =C PD V CC 2 f+i CC V CC C,V CC =5.0 V 0 pf

5 TIMING REQUIREMENTS (C L =50pF,Input t r =t f = ) V CC Symbol Parameter V C to -55 C t SU t SU t SU t h t h t rec t rec Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) Minimum Setup Time, Load to Clock (Figure 4) Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) Minimum Hold Time, Clock to Load or Preset Data Inputs (Figure 4) Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Recovery Time, Load Inactive to Clock (Figure 4) t w Minimum Pulse Width, Clock (Figure 1) t w Minimum Pulse Width, Reset (Figure 2) t r, t f Maximum Input Rise and Fall Times (Figure 1) Guaranteed Limit 85 C 1 C Unit

6 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit

7 V CC =Pin GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. Figure 7.Expanded logic diagram

8 Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve.. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram

9 TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configuratio the clock f max guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter

10 N SUFFIX PLASTIC DIP (MS - 001BB) NOTES: 1 A G F 0. (0.010) M T 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0. mm (0.010) per side. 9 8 D N B -T- C -T- K SEATING PLANE M L H J Dimeion, mm Symbol MIN MAX A B C 5. D F G H J 0 10 K L M N 0.8 D SUFFIX SOIC (MS - 0AC) H 1 D G A 0. (0.010) M T C M 9 8 B K P C SEATING PLANE Symbol MIN MAX A B.8 4 C D F G H Dimeion, mm J 0 8 NOTES: K Dimeio A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion 0. mm (0.006) per side P for A; for B 0. mm (0.010) per side. R J R x 45 F M

Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS

TECHNICAL DATA IN74HC193A Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS The IN74HC193A is identical in pinout to the LS/ALS193. The device inputs are compatible with standard