MM74HC595 8-Bit Shift Register with Output Latches

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1 MM74HC595 8-Bit Shift Register with Output Latches Features Low Quiescent current: 80µA Maximum (74HC Series) Low Input Current: 1µA Maximum 8-Bit Serial-In, Parallel-Out Shift Register with Storage Wide Operating oltage Range: 2 6 Cascadable Shift Register has Direct Clear Guaranteed Shift Frequency: DC to 30MHz Description June 2009 The MM74HC595 high-speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power coumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contai an eight-bit serial-in, parallel-out, shift register that feeds an eight-bit D-type storage register. The storage register has eight 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a directoverriding clear, serial input, and serial output (standard) pi for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state is one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to CC and ground. Ordering Information Part Number Operating Temperature Range Eco Status Package Packing Method MM74HC595M -40 to +85 C RoHS 16-Lead, Small Outline Integrated Circuit (SOIC), Tubes MM74HC595MX -40 to +85 C RoHS JEDEC MS-012, Inch Narrow Tape and Reel MM74HC595SJ -40 to +85 C RoHS 16-Lead, Small Outline Package (SOP), EIAJ Tubes MM74HC595SJX -40 to +85 C RoHS TYPE II, 5.3mm Wide Tape and Reel MM74HC595MTC -40 to +85 C RoHS 16-Lead, Thin Shrink Small Outline Package Tubes MM74HC595MTCX -40 to +85 C RoHS (TSSOP), JEDEC MO-153, 4.4mm Wide Tape and Reel MM74HC595N -40 to +85 C RoHS 16-Lead, Plastic Dual In-Line Package (PDIP), JEDEC MS-001, Inch Wide For Fairchild s definition of Eco Status, please visit: Tubes MM74HC595 Rev

2 Block Diagram Figure 1. Logic Diagram (Positive Logic) MM74HC595 Rev

3 Pin Configuration Pin Definitio Pin # Name Description 1 Q B Output Bit B 2 Q C Output Bit C 3 Q D Output Bit D 4 Q E Output Bit E 5 Q F Output Bit F 6 Q G Output Bit G 7 Q H Output Bit H 8 GND Ground 9 Q H Serial Data Output 10 SCLR Shift Register Clear 11 SCK Shift Register Clock Input 12 RCK Storage Register Clock Input 13 G Output Enable 14 SER Serial Data Input 15 QA Output Bit A 16 CC Supply oltage Figure 2. Pin Configuration Truth Table RCK SCK SCLR G Function X X X H QA through Q H = 3-state X X L L Shift register clocked; Q H = 0 X H L Shift register clocked; Q N = Q n-1, Q 0 = SER X H L Contents of shift; register traferred to output latches L = Logic Level LOW H = Logic Level HIGH X = Don t Care = Traition from LOW to HIGH level MM74HC595 Rev

4 Absolute Maximum Ratings (1) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditio and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditio may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit CC Supply oltage IN DC Input oltage -1.5 to CC+ 1.5 OUT DC Output oltage -0.5 to CC+ 0.5 I IK, I OK Clamp Diode Current ±20 ma I OUT DC Output Current, per Pin ±35 ma I CC DC CC or GND Current, per Pin ±70 ma T STG Storage Temperature Range C P D Power Dissipation PDIP (2) 600 SOIC Package Only 500 mw T L Lead Temperature +260 C ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power dissipation temperature derating, plastic package (PDIP);12mW/ C from -65 to +85 C Recommended Operating Conditio The Recommended Operating Conditio table defines the conditio for actual device operation. Recommended operating conditio are specified to eure optimal performance to the datasheet specificatio. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit CC Supply oltage 2 6 IN, OUT DC Input or Output oltage 0 CC T A Operating Temperature Range C CC= t R,t F Input Rise and Fall Times CC= CC= MM74HC595 Rev

5 Electrical Characteristics (3) Symbol Parameter Conditio CC IH IL OH OL I IN I OZ I CC Minimum HIGH Level Input oltage Minimum LOW Level Input oltage Minimum HIGH Level Output oltage Q H IN= IH or IL Q A through Q H Minimum LOW Level Output oltage IN= IH or IL I OUT 20µA IN= IH or IL Q H IN= IH or IL Q A through Q H Maximum Input Output Leakage Maximum 3- State Output Leakage Maximum Quiescent Supply Current IN= IH or IL I OUT 20µA IN= IH or IL T A =25 C Typ. T A =-40 to 85 C T A =-55 to 125 C Guaranteed Limits I OUT 4.0mA I OUT 5.2mA I OUT 6.0mA I OUT 7.8mA I OUT 4.0mA I OUT 5.2mA I OUT 6.0mA I OUT 7.8mA Units IN= CC or GND 6.0 ±0.1 ±1.0 ±1.0 µa OUT = CC or GND G= IH 6.0 ±0.5 ±5.0 ±10 µa IN = CC or GND I OUT=µA µa Note: 3. For a power supply of 5 ±10%, the worst-case output voltages ( OH, and OL) occur for HC at 4.5. The 4.5 values should be used when designing with this supply. Worst-case IH and IL occur at CC = 5.5 and 4.5, respectively; IH value at 5.5 is The worst-case leakage current (I IN, I CC, and I OZ) occurs for CMOS at the higher voltage; so the 6.0 values should be used. MM74HC595 Rev

6 AC Electrical Characteristics CC = 5, T A = 25 C, t r = t f = 6. Symbol Parameter Conditio Typ. Guaranteed Limit Units f MAX Maximum Operating Frequency of SCK MHz t PHL,t PLH t PZH,t PZL t PHZ,t PLZ t S Maximum Propagation Delay, SCK to Q H Maximum Propagation Delay, RCK to Q A C L=45pF thru Q H Maximum Output Enable Time from G to Q A thru Q H Maximum Output Disable Time from G to Q A thru Q H R L=1kΩ, C L=45pF R L=1kΩ, C L=45pF Minimum Setup Time from SER to SCK 20 Minimum Setup Time from SCLR to SCK 20 Minimum Setup Time from SER to (4) RCK 40 t H Minimum Hold Time from SER to SCK 0 t W Minimum Pulse Width of SCK or RCK 16 Note: 4. This setup time eures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the storage register state will be one clock pulse behind the shift register. MM74HC595 Rev

7 Electrical Characteristics CC = , C L = 50pF, t r = t f =6 unless otherwise specified. Symbol Parameter Conditio CC f MAX t PHL,t PLH Maximum Operating Frequency Maximum Propagation Delay, SCK to Q H Maximum Propagation Delay, RCK to Q A thru Q H Maximum Propagation Delay, SCLR to Q H C L=50pF T A =25 C Typ. T A =-40 to 85 C T A =-55 to 125 C Guaranteed Limits C L=50pF C L=150pF C L=50pF C L=150pF C L=50pF C L=150pF C L=50pF C L=150pF C L=50pF C L=150pF C L=50pF C L=150pF C L=50pF R L=1kΩ CL=150pF Units t PZH,t PZL Maximum Output Enable Time from G to Q A thru Q H C L=50pF C L=150pF C L=50pF C L=150pF t PHZ,t PLZ Maximum Output Disable Time from G to Q A thru Q H R L=1kΩ, C L=50pF Continued on the following page MM74HC595 Rev

8 Electrical Characteristics CC = , C L = 50pF, t r = t f =6 unless otherwise specified. Symbol Parameter Conditio CC t S t R t S t H t W t R,t F t THL,t TLH C PD Minimum Setup Time from SER to SCK Minimum Removal Time from SCLR to SCK Minimum Setup Time from SCK to RCK Minimum Hold Time from SER to SCK Minimum Pulse Width of SCK or SCLR Maximum Input Rise and Fall Time, Clock Maximum Output Rise and Fall Time Q A-Q H Maximum Output Rise and Fall Time Q H R L=1kΩ, C L=50pF T A =25 C Typ. Power Dissipation Capacitance, Outputs G= CC 90 Enabled (5) G=GND 150 T A =-40 to 85 C T A =-55 to 125 C Guaranteed Limits C IN Maximum Input Capacitance pf C OUT Maximum Output Capacitance pf Note: 5. C PD determines the no load dynamic power coumption, P D = C PD 2 CC f + I CC CC, and the no load dynamic current coumption, I S = C PD CCf + I CC. Units pf MM74HC595 Rev

9 Timing Diagram Figure 3. Timing Diagram Note: 6. XXX Implies that the output is in 3-state mode. MM74HC595 Rev

10 Physical Dimeio 6.00 PIN ONE INDICATOR MAX (0.30) M A CBA B 1.75 LAND PATTERN RECOMMENDATION C SEE DETAIL A C (R0.10) (R0.10) (1.04) X 45 GAGE PLANE 0.36 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, ARIATION AC, ISSUE C. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P600X175-16AM F) DRAWING FILE NAME: M16ARE12. DETAIL A SCALE: 2:1 Figure Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-012, Inch Narrow Package drawings are provided as a service to customers coidering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specificatio do not expand the terms of Fairchild s worldwide terms and conditio, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: MM74HC595 Rev

11 Physical Dimeio Figure Lead, Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers coidering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specificatio do not expand the terms of Fairchild s worldwide terms and conditio, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: MM74HC595 Rev

12 Physical Dimeio 5.00± ± MTC16rev4 Figure Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers coidering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specificatio do not expand the terms of Fairchild s worldwide terms and conditio, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: MM74HC595 Rev

13 Physical Dimeio 2.54 A (0.40) TOP IEW MIN MAX A SIDE IEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 ARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16ERE1 Figure Lead, Plastic Dual In-Line Package (PDIP), JEDEC MS-001, Inch Wide Package drawings are provided as a service to customers coidering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specificatio do not expand the terms of Fairchild s worldwide terms and conditio, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: MM74HC595 Rev

14 MM74HC595 Rev

15 Mouser Electronics Authorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: MM74HC595M_Q MM74HC595N MM74HC595MTC_Q MM74HC595N_Q MM74HC595WM MM74HC595WMX

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high