74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs

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1 June 1998 Revised February LCX112 Low oltage Dual J-K Negative Edge-Triggered Flip-Flop with 5 Tolerant Inputs General Description The LCX112 is a dual J-K flip-flop. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs with Q, Q outputs. These devices are edge sensitive and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input. LCX devices are designed for low voltage (3.3 or 2.5) operation with the added capability of interfacing to a 5 signal environment. The 74LCX112 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Code: Features 5 tolerant inputs CC specifications provided 7.5 ns t PD max ( CC = 3.3), 10 µa I CC max Power down high impedance inputs and outputs ±24 ma output drive ( CC = 3.0) Implements patented noise/emi reduction circuitry Latch-up performance exceeds 500 ma ESD performance: Human body model > 2000 Machine model > 2000 Order Number Package Number Package Description 74LCX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, Narrow 74LCX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbol Pin Descriptions IEEE/IEC Connection Diagram 74LCX112 Low oltage Dual J-K Negative Edge-Triggered Flip-Flop with 5 Tolerant Inputs Pin Names J 1, J 2, K 1, K 2 CP 1, CP 2 C D1, C D2 S D1, S D2 Q 1, Q 2, Q 1, Q 2 Description Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs 2001 Fairchild Semiconductor Corporation DS

2 74LCX112 Truth Table (Each half) Inputs Outputs S D C D CP J K Q Q L H X X X H L H L X X X L H L L X X X H H H H h h Q O Q O H H l h L H H H h l H L H H l l Q O Q O H H H X X Q O Q O H(h) = HIGH oltage Level L(l) = LOW oltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q O (Q O ) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram 2

3 Absolute Maximum Ratings(Note 1) Symbol Parameter alue Conditions Units CC Supply oltage 0.5 to +7.0 I DC Input oltage 0.5 to +7.0 O DC Output oltage 0.5 to CC Output in HIGH or LOW State (Note 2) I IK DC Input Diode Current 50 I < GND ma I OK DC Output Diode Current 50 O < GND +50 O > CC ma I O DC Output Source/Sink Current ±50 ma I CC DC Supple Current per Supply Pin ±100 ma I GND DC Ground Current per Ground Pin ±100 ma T STG Storage Temperature 65 to 150 C 74LCX112 Recommended Operating Conditions (Note 3) Symbol Parameter Min Max Units CC Supply oltage Operating Data Retention I Input oltage O Output oltage HIGH or LOW State 0 CC I OH /I OL Output Current CC = ±24 CC = ±12 ma CC = ±8 T A Free-Air Operating Temperature C t/ Input Edge Rate, IN = , CC = ns/ Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Note 2: I O Absolute Maximum rating must be observed. Note 3: Unused Inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics CC T A = 40 C to +85 C Symbol Parameter Conditions () Min Max IH HIGH Level Input oltage IL LOW Level Input oltage OH HIGH Level Output oltage I OH = 100µA CC I OH = -8 ma I OH = 12 ma I OH = 18 ma I OH = 24 ma OL LOW Level Output oltage I OL = 100µA I OL = 8mA I OL = 12 ma I OL = 16 ma I OL = 24 ma I I Input Leakage Current 0 I I ±5.0 µa I OFF Power-Off Leakage Current I or O = µa I CC Quiescent Supply Current I = CC or GND µa 3.6 I ±10 µa I CC Increase in I CC per Input IH = CC µa Units 3

4 74LCX112 AC Electrical Characteristics T A = 40 C to 85 C, R L = 500Ω CC = 3.3 ± 0.3 CC = 2.7 CC = 2.5 ± 0.2 Symbol Parameters C L =50 pf C L = 50 pf C L =30 pf Units Min Max Min Max Min Max f MAX Maximum Clock Frequency MHz t PHL Propagation Delay ns t PLH CP n to Q n or Q n t PHL Propagation Delay ns t PLH C Dn or S Dn to Q n or Q n t S Setup Time ns t H Hold Time ns t W Pulse Width CP ns t W Pulse Width (C D, S D ) ns t REC Recovery Time ns t OSHL Output to Output Skew 1.0 ns t OSLH (Note 4) 1.0 Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ), or LOW-to-HIGH (t OSLH ). Dynamic Switching Characteristics CC T A = 25 C Symbol Parameter Conditions () Typical OLP Quiet Output Dynamic Peak OL C L = 50 pf, IH = 3.3, IL = C L = 30 pf, IH = 2.5, IL = OL Quiet Output Dynamic alley OL C L = 50 pf, IH = 3.3, IL = C L = 30 pf, IH = 2.5, IL = Units Capacitance Symbol Parameter Conditions Typical Units C IN Input Capacitance CC = Open, I = 0 or CC 7 pf C OUT Output Capacitance CC = 3.3, I = 0 or CC 8 pf C PD Power Dissipation Capacitance CC = 3.3, I = 0 or CC, f = 10 MHz 25 pf 4

5 AC Loading and Waveforms Generic for LCX Family 74LCX112 FIGURE 1. AC Test Circuit (C L includes probe and jig capacitance) Test Switch t PLH, t PHL Open t PZL, t PLZ 6 at CC = 3.3 ± 0.3 CC x 2 at CC = 2.5 ± 0.2 t PZH,t PHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output Low Enable and Disable Times for Logic Propagation Delay, Pulse Width and t rec Waveforms Setup Time, Hold TIme and Recovery TIme for Logic 3-STATE Output High Enable and Disable TImes for Logic FIGURE 2. Waveforms (Input Pulse Characteristics; f=1mhz, t r =t f =3ns) t rise and t fall Symbol CC 3.3 ± ± 0.2 mi CC /2 mo CC /2 x OL OL OL y OH 0.3 OH 0.3 OH

6 74LCX112 Schematic Diagram Generic for LCX Family 6

7 Physical Dimensions inches (millimeters) unless otherwise noted 74LCX Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, Narrow Package Number M16A 7

8 74LCX112 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 8

9 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY 74LCX112 Low oltage Dual J-K Negative Edge-Triggered Flip-Flop with 5 Tolerant Inputs FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

10 Mouser Electronics Authorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: 74LCX112MTC_Q 74LCX112M_Q 74LCX112SJX 74LCX112SJ_Q

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