Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS

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June Lawrence
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1 TECHNICAL DATA IN74HC193A Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS The IN74HC193A is identical in pinout to the LS/ALS193. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH traitio on the clock inputs. This counter may be preset by entering the desired data on the P, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.both a Terminal Count Down (TC D ) and Terminal Count Up (TC U ) Outputs are provided to enable cascading of both up and down counting functio. The TC D output produces a negative going pulse when the counter underflows and TC U outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TC U and TC D outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: to V Low Input Current: 1. µa High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC193AN Plastic IN74HC193AD SOIC T A = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =V CC PIN 8 = GND Rev.

2 MAXIMUM RATINGS * Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND) -.5 to +7. V V IN DC Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V V OUT DC Output Voltage (Referenced to GND) -.5 to V CC +.5 V I IN DC Input Current, per Pin ±2 ma I OUT DC Output Current, per Pin ±25 ma I CC DC Supply Current, V CC and GND Pi ±5 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to +15 C T L Lead Temperature, 1 mm from Case for 1 Seconds (Plastic DIP or SOIC Package) 75 5 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 1 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC DC Supply Voltage (Referenced to GND) V V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) V CC V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) V CC = V V CC = V V CC = V This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be cotrained to the range GND (V IN or V OUT ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Rev.

3 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditio V 25 C to -55 C V IH Minimum High- Level Input Voltage V IL Maximum Low - Level Input Voltage V OH Minimum High- Level Output Voltage V OUT =.1 V or V CC -.1 V I OUT 2 µa V OUT =.1 V or V CC -.1 V I OUT 2 µa V IN =V IH or V IL I OUT 2 µa V CC Guaranteed Limit C C Unit V V V V IN =V IH or V IL I OUT 4. ma I OUT 5.2 ma V OL Maximum Low- Level Output Voltage V IN =V IH or V IL I OUT 2 µa V V IN =V IH or V IL I OUT 4. ma I OUT 5.2 ma I IN I CC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) V IN =V CC or GND ±.1 ±1. ±1. µa V IN =V CC or GND I OUT =µa µa FUNCTION TABLE Inputs Mode MR PL CP U CP D H X X X Reset(Asyn.) L L X X Preset(Asyn.) L H H No Count L H H Count Up L H H Count Down L H H No Count X = don t care The IN74HC193 is an UP/DOWN MODULO- 16 Binary Counter. Logic equatio For Terminal Count: TC U = Q Q 1 Q 2 Q 3 CP U TC D = Q Q 1 Q 2 Q 3 CP D Rev.

4 AC ELECTRICAL CHARACTERISTICS (C L =5pF,Input t r =t f = ) Symbol Parameter V 25 C to -55 C f max t PLH, t PHL t PLH, t PHL t PLH, t PHL t TLH, t THL Minimum Clock Frequency (5% Duty Cycle) (Figures 1 and 6) Maximum Propagation Delay, Clock to Q (Figures 1 and 6) Maximum Propagation Delay, PL to Q (Figures 3 and 6) Maximum Propagation Delay, Clock to Terminal Count (Figures 2 and 6) Maximum Output Traition Time,Any Output (Figures 1 and 6) V CC Guaranteed Limit 85 C 125 C Unit C IN Maximum Input Capacitance pf MHz C PD Power Dissipation Capacitance (Per Package) C,V CC =5. V Used to determine the no-load dynamic power 6 pf coumption: P D =C PD V 2 CC f+i CC V CC TIMING REQUIREMENTS (C L =5pF,Input t r =t f = ) V CC Guaranteed Limit Symbol Parameter V 25 C to -55 C 85 C 125 C Unit t su t h t w t w t w t r, t f Minimum Setup Time, Pn to PL (Figure 4) Minimum Hold Time, Pn to PL (Figure 4) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, PL (Figure 3) Minimum Pulse Width, MR (Figure 5) Minimum Input Rise and Fall Times (Figure 1) Rev.

5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit Rev.

6 TIMING DIAGRAM Rev.

7 EXPANDED LOGIC DIAGRAM Rev.

8 N SUFFIX PLASTIC DIP (MS - 1BB) NOTES: 16 1 A G F.25 (.1) M T 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio.25 mm (.1) per side. 9 8 D N B -T- C -T- K SEATING PLANE M L H J Dimeion, mm Symbol MIN MAX A B C 5.33 D F G H J 1 K L M.2.36 N.38 D SUFFIX SOIC (MS - 12AC) H 16 1 D G A.25 (.1) M T C M 9 8 B K P C SEATING PLANE Symbol MIN MAX A B C D F G H Dimeion, mm J 8 NOTES: K Dimeio A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion.15 mm (.6) per side P for A; for B.25 mm (.1) per side. R.25.5 J R x 45 F M Rev.

Presettable Counters High-Performance Silicon-Gate CMOS

TECHNICAL DATA IN74HC1A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HC1A is identical in pinout to the LS/ALS1. The device inputs are compatible with standard CMOS outputs; with pullup