74VHC74 Dual D-Type Flip-Flop with Preset and Clear

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74HC74 Dual D-Type Flip-Flop with Preset and Clear General Description Ordering Code: October 1992 Revised March 1999 The HC74 is an advanced high speed CMOS Dual D- Type Flip-Flop fabricated with

1 74HC74 Dual D-Type Flip-Flop with Preset and Clear General Description Ordering Code: October 1992 Revised March 1999 The HC74 is an advanced high speed CMOS Dual D- Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is traferred to the Q output during the positive going traition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. An input protection circuit eures that 0 to 7 can be applied to the input pi without regard to the supply voltage. This device can be used to interface 5 to 3 systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features High Speed: f MAX = 170 MHz (typ) at T A = 25 C High noise immunity: NIH = NIL = 28% CC (min) Power down protection is provided on all inputs Low power dissipation: I CC = 2 µa (max) at T A = 25 C Pin and function compatible with 74HC74 Order Number Package Number Package Description 74HC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow 74HC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74HC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74HC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering code. 74HC74 Dual D-Type Flip-Flop with Preset and Clear Logic Symbol Connection Diagram IEEE/IEC Pin Descriptio Pin Names D 1, D 2 CK 1, CK 2 CLR 1, CLR 2 PR 1, PR 2 Q 1, Q 1, Q 2, Q 2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Preset Inputs Output Truth Table Inputs Outputs CLR PR D CK Q Q Function L H X X L H Clear H L X X H L Preset L L X X H (Note 1) H (Note 1) H H L L H H H H H L H H X Q n Q n No Change Note 1: This configuration is notable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) state Fairchild Semiconductor Corporation DS prf

2 74HC74 Absolute Maximum Ratings(Note 2) Supply oltage ( CC ) 0.5 to +7.0 DC Input oltage ( IN ) 0.5 to +7.0 DC Output oltage ( OUT ) 0.5 to CC Input Diode Current (I IK ) 20 ma Output Diode Current (I OK ) ±20 ma DC Output Current (I OUT ) ±25 ma DC CC /GND Current (I CC ) ±50 ma Storage Temperature (T STG ) 65 C to +150 C Lead Temperature (T L ) Soldering (10 seconds) 260 C DC Electrical Characteristics Recommended Operating Conditio (Note 3) Supply oltage ( CC ) 2.0 to 5.5 Input oltage ( IN ) 0 to +5.5 Output oltage ( OUT ) 0 to CC Operating Temperature (T OPR ) 40 C to +85 C Input Rise and Fall Time (t r, t f ) CC = 3.3 ± / CC = 5.0 ± / Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specificatio should be met, without exception, to eure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specificatio. Note 3: Unused inputs must be held HIGH or LOW. They may not float. T Symbol Parameter CC A = 25 C T A = 40 C to +85 C () Min Typ Max Min Max IH HIGH Level Input Units Conditio oltage CC 0.7 CC IL LOW Level Input oltage CC 0.3 CC OH HIGH Level Output IN = IH I OH = 50 µa oltage or IL I OH = 4 ma I OH = 8 ma OL LOW Level Output IN = IH I OL = 50 µa oltage or IL I OL = 4 ma I OL = 8 ma I IN Input Leakage Current ±0.1 ±1.0 µa IN = 5.5 or GND I CC Quiescent Supply Current µa IN = CC or GND 2

3 AC Electrical Characteristics Symbol Parameter T CC A = 25 C T A = 40 C to +85 C () Min Typ Max Min Max Units Conditio f MAX Maximum Clock 3.3 ± MHz Frequency C L = 50 pf 5.0 ± MHz C L = 50 pf t PLH Propagation Delay 3.3 ± t PHL Time (CK-Q, Q) C L = 50 pf 5.0 ± C L = 50 pf t PLH Propagation Delay Time 3.3 ± t PHL (CLR, PR -Q, Q) C L = 50 pf 5.0 ± C L = 50 pf C IN Input Capacitance pf CC = Open C PD Power Dissipation 25 pf (Note 4) Capacitance Note 4: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained from the equation: I CC (opr.) = C PD * CC * f IN + I CC /2 (per F/F). 74HC74 AC Operating Requirements CC T A = 25 C T A = 40 C to +85 C Symbol Parameter () Typ Guaranteed Minimum (Note 5) t W (L) Minimum Pulse Width (CK) t W (H) t W (L) Minimum Pulse Width (CLR, PR) t S Minimum Setup Time t H Minimum Hold Time t REC Minimum Recovery Time (CLR, PR) Note 5: CC is 3.3 ± 0.3 or 5.0 ± Units 3

4 74HC74 Physical Dimeio inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 4

5 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 74HC74 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 5

6 74HC74 Dual D-Type Flip-Flop with Preset and Clear Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio.

74VHC393 Dual 4-Bit Binary Counter

74VHC393 Dual 4-Bit Binary Counter Dual 4-Bit Binary Counter General Description March 1993 Revised March 1999 The HC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high