8-Input NAND Gate IN74HC30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00
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1 TENIL T IN743 8-Input NN ate The IN743 is high-speed Si-gate MOS device and is compatible with low power Schottky TTL (LSTTL). The device provide the 8-input NN function. Outputs irectly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent: 1. µ igh Noise Immunity haracteristic of MOS evices ORERIN INORMTION IN743N Plastic IN743 SOI T = for all packages LOI IRM E Y PIN SSINMENT E N 7 8 Y PIN 14 = PIN 7 = N UNTION TLE Inputs Output С E Y L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L X X X X X X X X L L X = don t care
2 IN743 MXIMUM RTINS* Symbol Parameter alue Unit Supply oltage (Referenced to N) -.5 to +7. IN Input oltage (Referenced to N) - to + OUT Output oltage (Referenced to N) -.5 to +.5 I IN Input urrent, per Pin ±2 m I OUT Output urrent, per Pin ±25 m I Supply urrent, and N Pi ±5 m P Power issipation in Still ir, Plastic IP** SOI Package** Tstg Storage Temperature -65 to +15 T L Lead Temperature, 1 mm from ase for 1 Seconds (Plastic IP or SOI Package) 75 5 *Maximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditio. **erating - Plastic IP: - 1 mw/ from 65 to 125 SOI Package: : - 7 mw/ from 65 to 125 mw 26 REOMMENE OPERTIN ONITIONS Symbol Parameter Min Max Unit Supply oltage (Referenced to N) IN, OUT Input oltage, Output oltage (Referenced to N) T Operating Temperature, ll Package Types t r, t f Input Rise and all Time (igure 1) = = = This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. or proper operation, IN and OUT should be cotrained to the range N ( IN or OUT ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either N or ). Unused outputs must be left open.
3 IN743 ELETRIL RTERISTIS (oltages Referenced to N) Symbol Parameter Test onditio I IL O OL I IL I I I Minimum igh-level Input oltage Maximum Low -Level Input oltage Minimum igh-level Output oltage Maximum Low-Level Output oltage Maximum Low-Level Input Leakage urrent Maximum igh-level Input Leakage urrent Maximum Quiescent Supply urrent (per Package) OUT or OUT - I OUT 2 µ OUT or OUT - I OUT 2 µ IN = I or IL I OUT - 2 µ I OUT m I OUT - 4. m I OUT m I OUT 2 µ 25 to uaranteed Limit Unit I OUT 2.4 m I OUT 4. m I OUT 5.2 m IN = µ IN = µ IN = or I OUT = µ 2 4 µ
4 IN743 ELETRIL RTERISTIS ( L =5p,Input t r =t f = ) Symbol Parameter 25 to -55 t PL, t PL Maximum Propagation elay (igure 1) t TL, t TL Maximum Output Traition Time (igure 1) uaranteed Limit Unit IN Maximum Input apacitance p P Power issipation apacitance (Per ate) Used to determine the no-load dynamic power coumption: P = P 2 f+i T =25, =5. 27 p t f t r Input N t PL t PL Output 2 2 t TL t TL = 1 =.5 2 igure 1. Switching Waveforms PULSE ENERTOR I R T EIE UNER TEST O L 5 p Termination resistance R T should be equal to Z OUT of pulse generators igure 2. Test ircuit
5 IN743 N SUIX PLSTI IP (MS - 1) NOTES: (.1) M T 1. imeio, do not include mold flash or protrusio. Maximum mold flash or protrusio.25 mm (.1) per side. 8 7 N -T- SETIN 5.27 PLNE K M J J 8.25 (.1) M T M NOTES: K imeio and do not include mold flash or protrusion. M Maximum mold flash or protrusion 5 mm (.6) per side P for ; for.25 mm (.1) per side. R T- K SETIN PLNE M L J imeion, mm Symbol MIN MX J 1 K L M.2.36 N.38 SUIX SOI (MS - 12) P Symbol MIN MX R x 45 imeion, mm 1.27
8-Input NAND Gate IN74HCT30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00
TENIL T IN74T3 8-Input NN ate The IN74T3 is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the 8-input NN function. Outputs irectly Interface
Dual 4-Input AND Gate
TENIAL DATA IN42A Dual 4-Input AND ate The IN42A is high-speed Si-gate MOS device and is pin compatible with pullup resistors with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND
Dual 4-Input AND Gate
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Triple 3-Input NOR Gate
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Dual J-K Flip-Flop with Set and Reset
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Dual D Flip-Flop with Set and Reset
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Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS
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Octal 3-State Noninverting Transparent Latch
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74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
MM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 7C/CT/CU/CMOS Logic Family Specifications The IC06 7C/CT/CU/CMOS Logic Package Information The IC06 7C/CT/CU/CMOS
M74HC4543TTR BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER
BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER HIGH SPEED: t PD = 14 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
74HC4051; 74HCT channel analog multiplexer/demultiplexer
Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
MC74HC4020A. 14-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS
M74H20A 4-Stage Binary Ripple ounter High Performance Silicon Gate MOS The M7420A is identical in pinout to the standard MOS M20B. The device inputs are compatible with standard MOS outputs; with pullup
74HC393; 74HCT393. Dual 4-bit binary ripple counter
Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR. tpd = 13 ns (TYP.
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR. HIGH SPEED tpd = 13 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) at T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE CAPABILITY