High Performance Silicon Gate CMOS
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- Beryl Pope
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1 SONUTOR TNL T igh Performance Silicon ate OS The 7078 is similar to the 078 metal gate OS device. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. Output rive apability: 0 LSTTL Loads Outputs irectly nterface to OS, NOS, and TTL Operating oltage Range: to 6 Low nput urrent: µ igh Noise mmunity haracteristic of OS evices n ompliance with the Requirements efined by Standard No. 7 hip omplexity: 0 Ts or 7. quivalent ates N SU PLST P S SU SO P S 7 0 ORRN NORTON 7N 7 Plastic SO LO R 0 PN SSNNT 0 = = N N N PN = PN 7 = N PNS 6, 8 = NO ONNTON N = NO ONNTON UNTON TL Outputs nputs through ll nputs L L ll Other ombinatio L 0/ otorola, nc. R 6
2 7078 U RTNS* SymbolÎ Parameter alue Unit ÎÎ Supply oltage (Referenced to N) 0. to ÎÎ ÎÎ in nput oltage (Referenced to N). to +. ÎÎ ÎÎ out Output oltage (Referenced to N) 0. to + 0. ÎÎ in nput urrent, per Pin ± 0 m ÎÎ out Output urrent, per Pin ± m ÎÎ Supply urrent, and N Pi ± 0 m ÎÎ P Power issipation in Still ir Plastic P 70 mw Î TstgÎÎ SO Package 00 Storage Temperature ÎÎ 6 to + 0 LÎÎ T Lead Temperature, mm from ase for 0 Seconds (Plastic P or SO Package) 60 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. or proper operation, in and out should be cotrained to the range N (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either N or ). Unused outputs must be left open. * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditio. erating Plastic P: 0 mw/ from 6 to SO Package: 7 mw/ from 6 to or high frequency or heavy load coideratio, see hapter of the otorola igh Speed OS ata ook (L/). RON OPRTN ONTONS Symbol Parameter in ax Unit Supply oltage (Referenced to N) 6.0 Î in, out nput oltage, Output oltage (Referenced to N) 0 T Operating Temperature, ll Package Types + tr, tf nput Rise and all Time = Î (igure ) = = LTRL RTRSTS (oltages Referenced to N) uaranteed Limit Î to Symbol Î Parameter Î Test onditio Î 8 Unit Î inimum igh Level nput Î out = 0. or 0. oltage out ÎÎ 0 µ L aximum Low Level nput Î out = 0. or 0. oltage out ÎÎ ÎÎ ÎÎ 0 µ Î.. O inimum igh Level Output in = or L Î Î oltage out 0 µ. ÎÎ..... ÎÎ in = or L out.0 m. out ÎÎ m Î OL aximum Low Level Output in = or L oltage out 0 µ. ÎÎ ÎÎ in = or L out.0 m. out ÎÎ m Î ÎÎ ÎÎ in aximum nput Leakage urrent in = or N 6.0 ± 0. ±.0 ±.0 µ Î aximum Quiescent Supply in = or N 6.0 urrent (per Package) Î out = 0 µ ÎÎ 0 0 µ NOT: nformation on typical parametric values can be found in hapter of the otorola igh Speed OS ata ook (L/). OTOROL igh Speed OS Logic ata L Rev 6
3 7078 LTRL RTRSTS (L = 0 p, nput tr = tf = 6 ) Î uaranteed Limit Î to SymbolÎ Parameter Î 8 Unit tpl, Î aximum Propagation elay, ny nput to Output ÎÎ Î 0 6 ÎÎ tpl (igures and ) tpl, aximum Propagation elay, ny nput to Output Î ÎÎ tpl (igures and ) Î 0 6 ttl, aximum Output Traition Time, ny Output Î ttl Î (igures,, and ). 7 0 ÎÎ in Î aximum nput apacitance p. or propagation delays with loads other than 0 p, see hapter of the otorola igh Speed OS ata ook (L/).. nformation on typical parametric values ran be found in hapter of the otorola igh Speed OS ata ook (L/). =.0 P Power issipation apacitance (Per {Package)* p * Used to determine the no load dynamic power coumption: P = P f +. or load coideratio, see hapter of the otorola igh Speed OS ata ook (L/). SWTN WORS N NPUT tpl OUTPUT ttl 0% tr 0% tf N tpl ttl N NPUT OUTPUT tr tpl ttl 0% 0% tf N tpl ttl igure. igure. TST PONT UNR TST OUTPUT L* * ncludes all probe and jig capacitance igure. Test ircuit igh Speed OS Logic ata L Rev 6 OTOROL
4 7078 PN LO R 0 OTOROL igh Speed OS Logic ata L Rev 6
5 7078 OUTLN NSONS 8 7 N STN PLN N SU PLST P P S SSU L L. LS WTN 0. (0.00) RUS O TRU POSTON T STN PLN T U TRL ONTON.. NSON L TO NTR O LS WN OR PRLLL.. NSON OS NOT NLU OL LS.. ROUN ORNRS OPTONL. NS LLTRS N N S. S L 0.00 S 7.6 S N STN PLN 7 8 P 7 PL PL 0. (0.00) T S S SU PLST SO P S 7 0 SSU 0. (0.00) R. NSONN N TOLRNN PR NS., 8.. ONTROLLN NSON: LLTR.. NSONS N O NOT NLU OL PROTRUSON.. U OL PROTRUSON 0. (0.006) PR S.. NSON OS NOT NLU R PROTRUSON. LLOWL R PROTRUSON SLL 0.7 (0.00) TOTL N SS O T NSON T U TRL ONTON. P R LLTRS N S 0.00 S NS N otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, nc. otorola, nc. is an qual Opportunity/ffirmative ction mployer. ow to reach us: US/UROP: otorola Literature istribution; PN: Nippon otorola Ltd.; Tatsumi SP L, Toshikatsu Otsuki, P.O. ox 0; Phoenix, rizona Seibu utsuryu enter, Tatsumi oto u, Tokyo, apan. 0 8 : R0@ .sps.mot.com TOUTON (60) 660 ON ON: otorola Semiconductors.. Ltd.; 8 Tai Ping ndustrial Park, NTRNT: NT.com Ting ok Road, Tai Po, N.T., ong ong igh Speed OS Logic ata L Rev 6 OLN 7078/ OTOROL
High Performance Silicon Gate CMOS
SEONDUTOR TEHNAL HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs.
High Performance Silicon Gate CMOS
SEIONDUTOR TENI DT igh Performance Silicon ate OS The 5/7T00 may be used as a level converter for interfacing TT or NOS outputs to high speed OS inputs. The T00 is identical in pinout to the S00. Output
High Performance Silicon Gate CMOS
SEIONDUTOR TEHNIAL DATA HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with
High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
SEONDUTOR TEHN DT High Performance Silicon Gate OS The 7HU0 is identical in pinout to the S0 and the 069UB. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible
With LSTTL Compatible Inputs High Performance Silicon Gate CMOS
SEIONDUTOR TEHNI DT With STT ompatible Inputs High Performance Silicon Gate OS The 74HT04 may be used as a level converter for interfacing TT or NOS outputs to High Speed OS inputs. The HT04 is identical
High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
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SEMICONDUCTOR TECHNICAL DATA
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Figure 1. Pinout: 16 Lead Packages Conductors (Top View) ORDERING INFORMATION Figure 2. Logic Symbol PIN ASSIGNMENT
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High Performance Silicon Gate CMOS
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