High Performance Silicon Gate CMOS
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- Moris Palmer
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1 SEIONDUTOR TENI DT igh Performance Silicon ate OS The 5/7T00 may be used as a level converter for interfacing TT or NOS outputs to high speed OS inputs. The T00 is identical in pinout to the S00. Output Drive apability: 0 STT oads TT/NOS ompatible Input evels Outputs Directly Interface to OS, NOS and TT Operating oltage Range: to 5.5 ow Input urrent:.0 µ In ompliance with the Requirements Defined by EDE Standard No. 7 hip omplexity: 8 ETs or Equivalent ates SUIX ERI PE SE 6 08 N SUIX PSTI PE SE D SUIX SOI PE SE 75 0 ORDERIN INORTION OI DIR Y 6 Y Y = 8 Y Y 5TXX 7TXXN 7TXXD PIN SSINENT Y Y eramic Plastic SOI Y PIN = PIN 7 = ND ND 7 8 Y UNTION TE Inputs Output Y 0/95 otorola, Inc. 995 RE 6
2 5/7T00 XIU RTINS* Symbol Parameter alue Unit D Supply oltage (Referenced to ND) 0.5 to in D Input oltage (Referenced to ND) 0.5 to out D Output oltage (Referenced to ND) 0.5 to I in D Input urrent, per Pin ± 0 m I out D Output urrent, per Pin ± 5 m I D Supply urrent, and ND Pins ± 50 m D P Power Dissipation in Still ir, Plastic or eramic DIP 750 mw Tstg SOI Package 500 Storage Temperature 65 to + 50 T ead Temperature, mm from ase for 0 Seconds SOI or Plastic Package 60 eramic Dip * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditions. Derating Plastic DIP: 0 mw/ from 65 to 5 eramic DIP: 0 mw/ from 00 to 5 SOI Package: 7 mw/ from 65 to 5 or high frequency or heavy load considerations, see hapter of the otorola igh Speed OS Data ook (D9/D). REOENDED OPERTIN ONDITIONS Symbol Parameter in ax Unit Î D Supply oltage (Referenced to ND) in, out D Input oltage, Output oltage (Referenced to ND) 0 Î T Operating Temperature, ll Package Types Î tr, tf Input Rise and all Time (igure ) ns Î Î Î Î D RTERISTIS OR TE 5/7T00 (oltages Referenced to ND) uaranteed imits Î 55 to 5 85 Î 5 Symbol Parameter Test onditions in ax in ax in ax Unit I inimum igh evel out = 0. or 0. Input oltage Iout µ I aximum ow evel out = 0. or 0. Input oltage Iout 0 µ O inimum igh evel in = I or I Output oltage Iout µ in = I or I Iout.0 m O Î aximum ow evel in = I or I Î Output oltage Iout 0 µ 5.5 in = I or I Î Î Iout =.0 m I in aximum Input eakage in = or ND urrent 5.5 ± ±.00 ±.00 µ I aximum Quiescent Sup- in = or ND ply urrent (per Package) Iout 5.5 Î 0 0 µ Î 0 µ I dditional Quiescent in =., ny One Input Î 55 5 to 5 Supply urrent in = or ND, Other Inputs lout = 0 µ Î m NOTE: Information on typical parametric values can be found in hapter of the otorola igh Speed OS Data ook (D9/D). 00 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. or proper operation, in and out should be constrained to the range ND (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or ). Unused outputs must be left open. OTORO igh Speed OS ogic Data D9 Rev 6
3 5/7T00 RTERISTIS OR TE 5/7T00 ( = 5.0 ± 0%, = 50 p, Input tr = tf = 6.0 ns) Î uaranteed imits 55 to 5 85 Î 5 Î Symbol Parameter ig. Î in ax in ax in ax Î Unit tp, aximum Propagation Delay, Input, 9 8 ns tp or to Output Y Î Î Î tt, aximum Output Transition, 5 9 Î ns tt Time, ny Output Î in aximum Input apacitance Î p NOTE: or propagation delays with loads other than 50 p, and information on typical parametric values, see hapter of the otorola igh Speed OS Data ook (D9/D). 5, = 5.0 PD Power Dissipation apacitance (Per ate)* 5 p * Used to determine the no load dynamic power consumption: PD = PD f + I. or load considerations, see hapter of the otorola igh Speed OS Data ook (D9/D). INPUT OR OUTPUT Y 90%. 0% 90%. 0% tf tp tr tp.0 ND DEIE UNDER TEST OUTPUT TEST POINT * tt tt * Includes all probe and jig capacitance igure. Switching Waveforms igure. Test ircuit EXPNDED OI DIR (/ O TE DEIE) Y igh Speed OS ogic Data D9 Rev 6 OTORO
4 5/7T T- SETIN PNE OUTINE DIENSIONS SUIX ERI DIP PE SE 6 08 ISSUE Y N D P P 0.5 (0.00) T S 0.5 (0.00) T S. DIENSIONIN ND TOERNIN PER NSI Y, 98.. ONTROIN DIENSION: IN.. DIENSION TO ENTER O ED WEN ORED PRE.. DIESNION Y NRROW TO 0.76 (0.00) WERE TE ED ENTERS TE ERI ODY. DI D N INES IN X S S IIETERS IN X S S D N SETIN PNE N SUIX PSTI DIP PE SE ISSUE. EDS WITIN 0. (0.005) RDIUS O TRUE POSITION T SETIN PNE T XIU TERI ONDITION.. DIENSION TO ENTER O EDS WEN ORED PRE.. DIENSION DOES NOT INUDE OD S.. ROUNDED ORNERS OPTION. INES IIETERS DI IN X IN X D S.5 S S 7.6 S N SETIN PNE 7 8 P 7 P D P 0.5 (0.00) T S S D SUIX PSTI SOI PE SE 75 0 ISSUE 0.5 (0.00) R X 5. DIENSIONIN ND TOERNIN PER NSI Y, 98.. ONTROIN DIENSION: IIETER.. DIENSIONS ND DO NOT INUDE OD PROTRUSION.. XIU OD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIENSION D DOES NOT INUDE DR PROTRUSION. OWE DR PROTRUSION S E 0.7 (0.005) TOT IN EXESS O TE D DIENSION T XIU TERI ONDITION. DI D P R IIETERS IN X S S INES IN X OTORO igh Speed OS ogic Data D9 Rev 6
5 5/7T00 otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. ow to reach us: US/EUROPE: otorola iterature Distribution; PN: Nippon otorola td.; Tatsumi SPD D, Toshikatsu Otsuki, P.O. ox 09; Phoenix, rizona Seibu utsuryu enter, Tatsumi oto u, Tokyo 5, apan X: RX0@ .sps.mot.com TOUTONE (60) 6609 ON ON: otorola Semiconductors.. td.; 8 Tai Ping Industrial Park, INTERNET: NET.com 5 Ting ok Road, Tai Po, N.T., ong ong igh Speed OS ogic Data D9 Rev 6 ODEINE 5/7T00/D 5 OTORO
With LSTTL Compatible Inputs High Performance Silicon Gate CMOS
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High Performance Silicon Gate CMOS
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Is Now Part of To learn more about ON Semiconductor, please visit our website at
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC
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OS LSI L L Digital to Analog onverters with Serial Interface Legacy Device: otorola/reescale, The L and L are low cost 6 bit D/A converters with serial interface ports to provide communication with OS
MC74LCX138MEL. With 5 V Tolerant Inputs
With 5 V Tolerant Inputs The MC74LCX38 is a high performance, 3 to 8 decoder/demultiplexer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading
High Performance Silicon Gate CMOS
High Performance Silicon Gate CMOS The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT14A is identical in pinout to the LS14. The HCT14A
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW
The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data
MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
MC3346. General Purpose Transistor Array One Differentially Connected Pair and Three Isolated Transistor Arrays
General Purpose Transistor Array One Differentially Connected Pair and Three Isolated Transistor Arrays The MC336 is designed for general purpose, low power applications for consumer and industrial designs.
The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.
The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
with LSTTL Compatible Inputs
with STT Compatible Inputs The MC74HC259 is an 8 bit Addressable atch fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT devices while
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The 74HCT245 is identical in pinout to LS245. The device has TTL-Compatible Inputs. The HCT245
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS
TECNICAL DATA Octal 3-State Noninverting Buffer/Line Driver/Line Receiver igh-performance Silicon-ate CMOS IN74CT244A The IN74CT244A is identical in pinout to the LS/ALS244. The device may be used as a
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
Dual 4-Input AND Gate
TENIAL DATA IN42A Dual 4-Input AND ate The IN42A is high-speed Si-gate MOS device and is pin compatible with pullup resistors with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in
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NL27WZU04. Dual Unbuffered Inverter
Dual Unbuffered Inverter The N27WZU04 is a high performance dual unbuffered inverter operating from a.5 to 5.5 V supply. These devices are well suited for use as oscillators, pulse shapers, and in many
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1. JFET Switching Transistors. N Channel. Pb Free Packages are Available.
LT1, LT1, LT1 JFET Switching Transistors NChannel Features PbFree Packages are Available MAXIMUM RATINGS Rating Symbol Value Unit DrainSource Voltage V DS Vdc DrainGate Voltage V DG Vdc GateSource Voltage