MC74HCT366A. Hex 3-State Inverting Buffer with Common Enables and LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

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1 ex 3-State Inverting Buffer with Common Enables and STT Compatible Inputs igh Performance Silicon Gate CMOS The MC74CT366A is identical in pinout to the S366. The device inputs are compatible with standard CMOS or STT outputs. This device is a high speed hex buffer with 3 state outputs and two common active low Output Enables. When either of the enables is high, the buffer outputs are placed into high impedance states. The CT366A has inverting outputs. Features Output Drive Capability: 5 STT oads Outputs Directly Interface to CMOS, NMOS, and TT Operating oltage Range: to ow Input Current:. A igh Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 9 FETs or 22.5 Equivalent Gates These are Pb Free Devices* 6 6 SOIC 6 D SUFFI CASE 75B TSSOP 6 DT SUFFI CASE 948F 6 MARKING DIAGRAMS CT366AG AWYWW 6 CT 366A AYW A = Assembly ocation W, = Wafer ot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. Semiconductor Components Industries, C, 2 January, 2 Rev. Publication Order Number: MC74CT366A/D

2 ENABE A Y ENABE 2 A5 A A Y Y A Y Y5 A4 A2 6 7 Y2 A2 Y2 6 7 Y4 A3 A3 9 Y3 GND 8 9 Y3 A4 2 Y4 Figure. Pin Assignment A5 4 3 Y5 Enable FUNCTION TABE Inputs = don t care Z = high impedance Output Enable 2 A Y Z Z ENABE ENABE 2 5 Figure 2. ogic Diagram PIN 6 = PIN 8 = GND ORDERING INFORMATION MC74CT366ADG Device Package Shipping SOIC 6 (Pb Free) 48 Units / Rail MC74CT366ADR2G SOIC 6 (Pb Free) 25 Units / Reel MC74CT366ADTR2G TSSOP 6* 25 Units / Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD8/D. *This package is inherently Pb Free. 2

3 MAIMUM RATINGS* Symbol Parameter alue Unit DC Supply oltage (Referenced to GND).5 to + 7. in DC Input oltage (Referenced to GND).5 to +.5 out DC Output oltage (Referenced to GND).5 to +.5 I in DC Input Current, per Pin ± 2 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and GND Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package 5 45 T stg Storage Temperature 65 to + 5 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. Derating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C mw This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time = (Figure ) = = = DC EECTRICA CARACTERISTICS (oltages Referenced to GND) Symbol Parameter Test Conditio I I O O Minimum igh evel Input oltage Maximum ow evel Input oltage Minimum igh evel Output oltage Maximum ow evel Output oltage out =. I out 2 μa out =. I out 2 μa in = I I out 2 μa in = I in = I I out 2 μa in = I I out 3.6 ma I out ma I out 7.8 ma I out 3.6 ma I out ma I out 7.8 ma to 5.5 to 5.5 Guaranteed imit 55 to 25 C 85 C 25 C Unit I in Maximum Input eakage Current in = or GND ±. ±. ±. μa

4 DC EECTRICA CARACTERISTICS (oltages Referenced to GND) Symbol I OZ I CC Parameter Maximum Three State eakage Current Maximum Quiescent Supply Current (per Package) Test Conditio Output in igh Impedance State in = I or I out = or GND in = or GND I out = μa 55 to 25 C Guaranteed imit 85 C 25 C Unit ±.5 ± 5. ± μa μa AC EECTRICA CARACTERISTICS (C = 5 pf, Input t r = t f = 6 ) Symbol t P, t P t PZ, t PZ t PZ, t PZ t T, t T Parameter Maximum Propagation Delay, Input A to Output Y (Figures and 3) Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures and 3) Guaranteed imit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance pf C out Maximum Three State Output Capacitance (Output in igh Impedance State) Unit pf 25 C, = 5. C PD Power Dissipation Capacitance (Per Buffer)* * Used to determine the no load dynamic power coumption: P D = C PD 2 f + I CC. 6 pf 4

5 SWITCING WAEFORMS ( I = to 3, M =.3 ) INPUT A ( I ) Y t r t P t T % 9% M 9% 5% % t f t P t T GND ENABE ( I ) Y Y M 5% 5% t PZ t PZ t PZ t PZ % 9% GND IG IMPEDANCE O O IG IMPEDANCE Figure. Figure 2. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST C * DEICE UNDER TEST kω C * CONNECT TO WEN TESTING t PZ AND t PZ. CONNECT TO GND WEN TESTING t PZ AND t PZ. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Figure 4. OGIC DETAI TO OTER FIE BUFFERS ONE OF 6 BUFFERS Y INPUT A ENABE ENABE 2 5

6 PACKAGE DIMENSIONS TSSOP 6 DT SUFFI CASE 948F ISSUE B.5 (.6) T.5 (.6) T. (.4) T SEATING PANE U PIN IDENT. U D S S 2 /2 C 6 K REF. (.4) M T U S S A G B U N N J J F DETAI E DETAI E K K ÇÇÇ ÇÇÇ ÉÉ SECTION N N.25 (.) M SODERING FOOTPRINT W NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS. PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT ECEED.5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT ECEED.25 (.) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE.8 (.3) TOTA IN ECESS OF TE K DIMENSION AT MAIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MA MIN MA A B C.2.47 D F G.65 BSC.26 BSC J J K K BSC.252 BSC M PITC DIMENSIONS: MIIMETERS 6

7 PACKAGE DIMENSIONS SOIC 6 D SUFFI CASE 75B 5 ISSUE K A B P 8 P.25 (.) M B S NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAIMUM MOD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE.27 (.5) TOTA IN ECESS OF TE D DIMENSION AT MAIMUM MATERIA CONDITION. T SEATING PANE G K C D 6 P.25 (.) M T B S A S M R 45 J F MIIMETERS INCES DIM MIN MA MIN MA A B C D F G.27 BSC.5 BSC J K M 7 7 P R SODERING FOOTPRINT PITC 8 9 DIMENSIONS: MIIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any licee under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative MC74CT366A/D