MC74VHCT541A. Octal Bus Buffer

Transcription

1 Octal Bus Buffer The is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The is a noninverting, 3 state, buffer/line driver/line receiver. When either OE or OE2 is high, the terminal outputs are in the high impedance state. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5.0 CMOS level output swings. The CT54 input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. SOIC WB SUFFI DW CSE 75D MRKING DIGRMS CT54 WYYWWG Features igh Speed: t PD = 5.4 (Typ) at CC = 5.0 ow Power Dissipation: I CC = 4 (Max) at T = 25 C TT Compatible Inputs: I = 0.8 ; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for to 5.5 Operating Range ow Noise: OP =.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300 m ESD Performance: uman Body Model > 00 ; Machine Model > 0 Chip Complexity: 34 FETs or 33.5 Equivalent Gates N Prefix for utomotive and Other pplicatio Requiring Unique Site and Control Change Requirements; EC Q00 Qualified and PPP Capable These Devices are Pb Free, alogen Free/BFR Free and are RoS Compliant TSSOP SUFFI DT CSE 948E SOEIJ SUFFI M CSE 967 CT 54 YW 74CT54 WYWWG = ssembly ocation W, = Wafer ot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNCTION TBE Inputs OE OE2 Output Y Z Z ORDERING INFORMTION See detailed ordering and shipping information in the package dimeio section on page 4 of this data sheet. Semiconductor Components Industries, C, 4 September, 4 Rev. 6 Publication Order Number: /D

2 2 8 Y Y2 6 Y3 OE 2 9 CC OE2 DT INPUTS Y4 4 Y5 NONINERTING OUTPUTS Y Y2 Y Y Y4 Y Y7 Y8 7 8 GND Y6 Y7 Y8 OUTPUT ENBES OE OE2 9 Figure 2. Pin ssignment Figure. ogic Diagram MIMUM RTINGS alue Unit CC DC Supply oltage 0.5 to in DC Input oltage 0.5 to Î out DC Output oltage Outputs in 3 State 0.5 to igh or ow State 0.5 to CC Î I IK Input Diode Current m Î I OK Output Diode Current ( OUT < GND; OUT > CC ) ± m Î I out DC Output Current, per Pin ± 25 m Î I CC DC Supply Current, CC and GND Pi ± 75 m Î P D Power Dissipation in Still ir, SOIC Package 500 TSSOP Package 450 mw T Î stg Storage Temperature 65 to + 50 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating SOIC Packages: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. RECOMMENDED OPERTING CONDITIONS Î Î Min Î Max Unit Î CC Î DC Supply oltage Î 5.5 Î in Î DC Input oltage 0 Î 5.5 Î out Î DC Output oltage Outputs in 3 State Î igh or ow State Î CC Î T Î Operating Temperature 40 Î + 85 C Î t r, t f Î Input Rise and Fall Time CC =5.0 ±0.5 0 Î / Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2

3 Î DC EECTRIC CRCTERISTICS Î CC T = 25 C T = 40 to 85 C Î Î Î Test Conditio Î Min Typ Max Min Î Max Unit I Minimum igh evel Input oltage to 5.5 Î Î Î Î Î I Maximum ow evel Input oltage to Î Î O Minimum igh evel Output I Î oltage in = I or I O = 50 Î Î Î I O = 8m 3.94 Î 3.80 O Maximum ow evel Output I Î oltage in = I or I O = Î Î 0. I O = 8m Î I in Maximum Input eakage Current in = 5.5 or GND 0 to 5.5 ± 0. ±.0 Î I Î OZ Maximum 3 State eakage Current Î in = I or I 5.5 ± 0.25 ± 2.5 out = CC or GND Î I CC Î Maximum Quiescent Supply Current in = CC or GND Î I CCT Î Quiescent Supply Current Per Input: IN Î = Î Other Input: CC or GND m Î I OPD Î Output eakage Current Î OUT = 5.5 Î Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio. Î C EECTRIC CRCTERISTICS (Input t r = t f = 3.0) Î T = 25 C T = 40 to 85 C Test Conditio Min Typ Max Min Max Unit Î t Î P, Maximum Propagation Delay, t P to Y CC = 5.0 ± 0.5 C = 5pF C = 50pF Î Î 9.0 Î t PZ, Output Enable TIme, CC = 5.0 ± 0.5 C = 5pF t Î PZ OE to Y R Î = k C = 50pF Î Î t PZ, t PZ Output Disable Time, CC = 5.0 ± 0.5 C = 50pF OE to Y R Î = k.0 Î 3.5 Î t Î OS, Output to Output Skew t OS Î CC = 5.0 ± 0.5 C = 50pF (Note ).0.0 Î Î C in Maximum Input Capacitance pf Maximum 3 State Output Capacitance 9 pf C out (Output in igh Impedance State) C PD Power Dissipation Capacitance (Note 2) 25 C, CC = 5.0. guaranteed by design. t OS = t Pm t Pn, t OS = t Pm t Pn. 2. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. verage operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC / 8 (per bit). C PD is used to determine the no load dynamic power coumption; P D = C PD CC 2 f in + I CC CC. NOISE CRCTERISTICS (Input t r = t f = 3.0, C = 50pF, CC = 5.0) 9 T = 25 C OP Quiet Output Maximum Dynamic O.2.6 O Quiet Output Minimum Dynamic O.2.6 ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0.8 Typ Max pf Unit 3

4 ORDERING INFORMTION DWG Device Package Shipping SOIC WB 38 Units / Rail DWRG DTG DTRG N74CT54DTRG* SOIC WB TSSOP TSSOP TSSOP 000 / Tape & Reel 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel MEG SOEIJ 00 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *N Prefix for utomotive and Other pplicatio Requiring Unique Site and Control Change Requirements; EC Q00 Qualified and PPP Capable. Y.5 t P t P.5 Figure 3. Switching Waveform OE or OE2.5 3 t PZ GND Y.5 O O Y.5 t PZ t PZ t PZ Figure 4. Switching Waveform 3 GND IG IMPEDNCE O +0.3 O -0.3 IG IMPEDNCE TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C * DEICE UNDER TEST OUTPUT k C * CONNECT TO CC WEN TESTING t PZ ND t PZ. CONNECT TO GND WEN TESTING t PZ ND t PZ. *Includes all probe and jig capacitance Figure 5. Test Circuit *Includes all probe and jig capacitance Figure 6. Test Circuit 4

5 PCKGE DIMENSIONS SOIC WB DW SUFFI CSE 75D 05 ISSUE G M B M D E h 45 NOTES:. DIMENSIONS RE IN MIIMETERS. 2. INTERPRET DIMENSIONS ND TOERNCES PER SME YM, DIMENSIONS D ND E DO NOT INCUDE MOD PROTRUSION. 4. MIMUM MOD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCUDE DMBR PROTRUSION. OWBE PROTRUSION S BE 0.3 TOT IN ECESS OF B DIMENSION T MIMUM MTERI CONDITION. B 0.25 M T S 8 e 0 B B S T SETING PNE C MIIMETERS DIM MIN M B C D E e.27 BSC h

6 PCKGE DIMENSIONS TSSOP CSE 948E 02 ISSUE C 0.5 (0.006) T 0.5 (0.006) T U 2 /2 PIN IDENT U S S C 0.00 (0.004) T SETING PNE K REF 0.0 (0.004) M T U S S 0 D G B U J J K K ÍÍÍÍ ÍÍÍÍ SECTION N N N 0.25 (0.00) M N F DETI E DETI E NOTES:. DIMENSIONING ND TOERNCING PER NSI YM, CONTROING DIMENSION: MIIMETER. 3. DIMENSION DOES NOT INCUDE MOD FS, PROTRUSIONS OR GTE BURRS. MOD FS OR GTE BURRS S NOT ECEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTERED FS OR PROTRUSION. INTERED FS OR PROTRUSION S NOT ECEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DMBR PROTRUSION. OWBE DMBR PROTRUSION S BE 0.08 (0.003) TOT IN ECESS OF TE K DIMENSION T MIMUM MTERI CONDITION. 6. TERMIN NUMBERS RE SOWN FOR REFERENCE ONY. 7. DIMENSION ND B RE TO BE DETERMINED T DTUM PNE W. MIIMETERS INCES DIM MIN M MIN M B C D F G 0.65 BSC BSC W J J K K BSC BSC M SODERING FOOTPRINT PITC DIMENSIONS: MIIMETERS 6

7 PCKGE DIMENSIONS SOEIJ M SUFFI CSE 967 ISSUE e E E 0 Z D E Q M DETI P IEW P c NOTES:. DIMENSIONING ND TOERNCING PER NSI YM, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D ND E DO NOT INCUDE MOD FS OR PROTRUSIONS ND RE MESURED T TE PRTING INE. MOD FS OR PROTRUSIONS S NOT ECEED 0.5 (0.006) PER SIDE. 4. TERMIN NUMBERS RE SOWN FOR REFERENCE ONY. 5. TE ED WIDT DIMENSION (b) DOES NOT INCUDE DMBR PROTRUSION. OWBE DMBR PROTRUSION S BE 0.08 (0.003) TOT IN ECESS OF TE ED WIDT DIMENSION T MIMUM MTERI CONDITION. DMBR CNNOT BE OCTED ON TE OWER RDIUS OR TE FOOT. MINIMUM SPCE BETWEEN PROTRUSIONS ND DJCENT ED TO BE 0.46 ( 0.08). b 0.3 (0.005) M 0.0 (0.004) MIIMETERS INCES DIM MIN M MIN M b c D E e.27 BSC BSC E E M Q Z ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, C (SCIC) or its subsidiaries in the United States and/or other countries. SCIC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCIC s product/patent coverage may be accessed at Marking.pdf. SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any licee under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICTION ORDERING INFORMTION ITERTURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@oemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative /D