MC74VHCT244A. Octal Bus Buffer/Line Driver with 3-State Outputs

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1 Octal Bus Buffer/ine Driver with 3-State Outputs The M74VHT244A is an advanced high speed MOS octal bus buffer fabricated with silicon gate MOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining MOS low power dissipation. The M74VHT244A is a noninverting 3 state buffer, and has two active low output enables. This device is designed to be used with 3 state memory address drivers, etc. The VHT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V MOS level output swings. The VHT244A input and output (when disabled) structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/ output voltage mismatch, battery backup, hot insertion, etc. SOI WB SUFFIX DW ASE 75D MARKING DIAGRAMS VHT244A AWYYWWG Features High Speed: t PD = 5.6 ns (Typ) at V = 5.0 V ow Power Dissipation: I = 4.0 (Max) at T A = 25 TT ompatible Inputs: V I = 0.8 V; V IH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range ow Noise: V OP =. V (Max) Pin and Function ompatible with Other Standard ogic Families atchup Performance Exceeds 300 ma ESD Performance: Human Body Model > 00 V; Machine Model > 0 V hip omplexity: 2 FETs or 28 Equivalent Gates NV Prefix for Automotive and Other Applications Requiring Unique Site and ontrol hange Requirements; AE Q00 Qualified and PPAP apable These Devices are Pb Free and are RoHS ompliant TSSOP SUFFIX DT ASE 948E ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. VHT 244A AYW A = Assembly ocation W, = Wafer ot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) Semiconductor omponents Industries,, 4 May, 4 Rev. 9 Publication Order Number: M74VHT244A/D

2 A 2 8 YA A2 4 6 YA2 A3 6 4 YA3 DATA INPUTS A4 B YA4 YB NONINVERTING OUTPUTS B2 3 7 YB2 B3 5 5 YB3 B4 7 3 YB4 OUTPUT ENABES OEA OEB 9 Figure. ogic Diagram OEA V FUNTION TABE A 2 9 OEB Inputs Outputs YB4 3 8 YA OEA, OEB A, B YA, YB A2 4 YB3 5 A B4 YA2 B3 H H H X Z H H Z Z YB2 7 4 YA3 A4 8 3 B2 YB 9 2 YA4 GND 0 B Figure 2. Pin Assignment 2

3 Î MAXIMUM RATINGS Symbol Parameter Value Unit V D Supply Voltage 0.5 to +7.0 V V in D Input Voltage 0.5 to +7.0 V V out D Output Voltage Output in 3 State 0.5 to +7.0 V High or ow State 0.5 to V Î I IK Input Diode urrent ma Î I OK Output Diode urrent (V OUT < GND; V OUT > V ) ± ma Î I out D Output urrent, per Pin ±25 ma Î I D Supply urrent, V and GND Pins ±75 ma Î P D Power Dissipation in Still Air, SOI Packages 500 TSSOP Package 450 mw T stg Storage Temperature 65 to +50 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating SOI Packages: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GND (V in or V out ) V. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). Unused outputs must be left open. REOMMENDED OPERATING ONDITIONS Î Symbol Parameter Min Max Unit Î V D Supply Voltage V Î V in D Input Voltage V Î V out D Output Voltage Output in 3 State High or ow State Î V V T A Operating Temperature Î Î Input Rise and Fall Time V = 5.0 V ± 0.5 V Î 0 ns/v t r, t f Î D EETRIA HARATERISTIS Î Symbol Parameter Test onditions Î V T A = 25 T A = 40 to 85 T A = 85 to 25 V Min Typ Î Max Min Max Min Max Î Unit V IH Î Minimum High evel 4.5 to Input Voltage 5.5 Î 2.0 Î V V I Maximum ow evel Input Voltage Î Î 4.5 to Î 5.5 Î Î Î 0.8 Î 0.8 Î Î Î 0.8 V V OH Î Minimum High evel I OH = 50 Î 4.5 Î Î 4.4ÎV Output Voltage V in = V IH or V I I OH = 8 maî 4.5 Î 3.94 Î 3.80 Î 3.66Î V O Î Maximum ow evel I O = 50 Î Î V Output Voltage V in = V IH or V I I O = 8 maî I in Î Maximum Input V in = 5.5 V or GND Î Î eakage urrent Î 0 to 5.5 ±0. ±.0 ±.0 I OZ Î Maximum 3 State V in = V I or V IH Î 5.5 eakage urrent V out = V ±0.25 or GND ± Î I Maximum Quiescent V Î Supply urrent Î Î in = V or GND 5.5 Î Î Î 4.0 Î 40.0 Î Î Î 40.0 I T Î Quiescent Supply Per Input: V IN =3.4 VÎ ma urrent Other Input: V Î or GND Î I OPD Î Output eakage V OUT = 5.5 V Î 0 Î Î 0.5 Î 5.0 Î 0 urrent Î 3

4 Î A EETRIA HARATERISTIS (Input t r = t f = 3.0 ns) T A = 25 T A = 40 to 85 T A = to 25 SymbolÎ Parameter Test onditions Î Min TypÎ Max Min Î Max Î Min Max Unit t PH, Î Maximum V = 5.0 ± 0.5 V = 5 pf 5.4Î Î 8.5 Î ns t PH Propagation Delay Î A to YA or B to YB = 50 pf Î t PZ, Î Output Enable Time V = 5.0 ± 0.5 V = 5 pfî t PZH OEA to YA or OEB to Î YB R = k = 50 pfî Î Î Î ns t PZ, Output Disable Time V = 5.0 ± 0.5 V = 50 pf t PHZ Î OEA to YA or OEB to R = k 8.8Î Î.4 Î Î Î 4.5 Î ns YB t OSH, Output to Output V t OSH Î Skew = 5.0 ± 0.5 V = 50 pf.0 Î Î.0.0 ns (Note ) A EETRIA HARATERISTIS (Input t r = t f = 3.0 ns) Symbol Parameter 25, V = 5.0 V Min Typ Max PD Power Dissipation apacitance (Note 2) 8 pf in Maximum Input apacitance 4 0 Î pf out Maximum Three State Output apacitance (Output in High Impedance State) 9 Î pf. Parameter guaranteed by design. t OSH = t PHm t PHn, t OSH = t PHm t PHn. 2. PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I (OPR) = PD V f in + I / 8 (per bit). PD is used to determine the no load dynamic power consumption; P D = PD V 2 f in + I V. NOISE HARATERISTIS (Input t r = t f = 3.0 ns, = 50 pf, V = 5.0 V) Symbol Parameter T A = 25 V OP Quiet Output Maximum Dynamic V O 0.9. V V OV Quiet Output Minimum Dynamic V O 0.9. V V IHD Minimum High evel Dynamic Input Voltage 2.0 V V ID Maximum ow evel Dynamic Input Voltage 0.8 V Typ Max Unit Unit ORDERING INFORMATION M74VHT244ADWRG Device Package Shipping SOI WB (Pb Free) 000 / Tape & Reel M74VHT244ADTG 75 Units / Rail M74VHT244ADTRG TSSOP (Pb Free) 2500 / Tape & Reel NV74VHT244ADTRG* 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *NV Prefix for Automotive and Other Applications Requiring Unique Site and ontrol hange Requirements; AE Q00 Qualified and PPAP apable. 4

5 A or B t PH.5 V t PH 3 V GND YA or YB.5 V V OH V O Figure 3. Switching Waveform OEA or OEB YA or YB YA or YB.5 V.5 V.5 V t PZ t PZH t PZ t PHZ Figure 4. Switching Waveform 3 V GND HIGH IMPEDANE V O +0.3 V V OH -0.3 V HIGH IMPEDANE TEST POINT DEVIE UNDER TEST OUTPUT * *Includes all probe and jig capacitance Figure 5. Test ircuit TEST POINT DEVIE UNDER TEST OUTPUT k * ONNET TO V WHEN TESTING t PZ AND t PZ. ONNET TO GND WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance Figure 6. Test ircuit 5

6 PAKAGE DIMENSIONS TSSOP ASE 948E 02 ISSUE 0.5 (0.006) T 0.5 (0.006) T U 2X /2 PIN IDENT U S S 0.00 (0.004) T SEATING PANE X K REF 0.0 (0.004) M T U S V S 0 A V D G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SETION N N F DETAI E 0.25 (0.00) DETAI E SODERING FOOTPRINT M NOTES:. DIMENSIONING AND TOERANING PER ANSI Y4.5M, ONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INUDE MOD FASH, PROTRUSIONS OR GATE BURRS. MOD FASH OR GATE BURRS SHA NOT EXEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INUDE INTEREAD FASH OR PROTRUSION. INTEREAD FASH OR PROTRUSION SHA NOT EXEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SHA BE 0.08 (0.003) TOTA IN EXESS OF THE K DIMENSION AT MAXIMUM MATERIA ONDITION. 6. TERMINA NUMBERS ARE SHOWN FOR REFERENE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INHES DIM MIN MAX MIN MAX A B D F G 0.65 BS BS W H J J K K BS BS M PITH 6X X.26 DIMENSIONS: MIIMETERS 6

7 PAKAGE DIMENSIONS SOI WB DW SUFFIX ASE 75D 05 ISSUE G H 0X 0.25 M B M D E A h X 45 NOTES:. DIMENSIONS ARE IN MIIMETERS. 2. INTERPRET DIMENSIONS AND TOERANES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INUDE DAMBAR PROTRUSION. AOWABE PROTRUSION SHA BE 0.3 TOTA IN EXESS OF B DIMENSION AT MAXIMUM MATERIA ONDITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PANE MIIMETERS DIM MIN MAX A A B D E e.27 BS H h ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, (SI). SI owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SI s product/patent coverage may be accessed at Marking.pdf. SI reserves the right to make changes without further notice to any products herein. SI makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SI assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SI data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SI does not convey any license under its patent rights nor the rights of others. SI products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SI product could create a situation where personal injury or death may occur. Should Buyer purchase or use SI products for any such unintended or unauthorized application, Buyer shall indemnify and hold SI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SI was negligent regarding the design or manufacture of the part. SI is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBIATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative M74VHT244A/D