MC74HCT259A. 8-Bit Addressable Latch 1-of-8 Decoder with LSTTL Inputs. High Performance Silicon Gate CMOS

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1 MC74CT259A 8-Bit Addressable atch -of-8 ecoder with STT Inputs igh Performance Silicon Gate CMOS The MC74CT259A is identical in pinout to the S259. The device inputs are compatible with standard CMOS and STT outputs. The CT259A has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on ata In is written into the addressed latch. The addressed latch follows the data input with all non addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the ata or Address inputs. In the one of eight decoding or demultiplexing mode, the addressed output follows the state of ata In with all other outputs in the OW state. In the Reset mode all outputs are OW and unaffected by the address and data inputs. When operating the CT259A as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. Features Output rive Capability: 0 STT oads Outputs irectly Interface to CMOS, NMOS, and TT Operating oltage Range: 4.5 to 5.5 ow Input Current: A igh Noise Immunity Characteristic of CMOS evices These are Pb Free evices 6 6 A W, YY, Y WW, W G or SOIC 6 SUFFIX CASE 75B 6 TSSOP 6 T SUFFIX CASE 948F MARKING IAGRAMS CT259AG AWYWW 6 = Assembly ocation = Wafer ot = Year = Work Week = Pb Free Package CT 259A AYW (Note: Microdot may be in either location) PIN ASSIGNMENT A0 A A2 Q0 Q Q2 Q CC RESET ENABE ATA IN Q7 Q6 Q5 Q4 MOE SEECTION TABE Enable Reset Mode Addressable atch Memory 8 ine emultiplexer Reset ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, C, 20 April, 20 Rev. 3 Publication Order Number: MC74CT259A/

2 MC74CT259A ARESS INPUTS A0 A A2 ATA IN RESET ENABE 4 4 Q0 5 Q 6 Q2 7 Q3 9 Q4 0 Q5 Q6 2 Q7 PIN 6 = CC PIN 8 = NONINERTING OUTPUTS ATC SEECTION TABE Address Inputs C B A atch Addressed Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 Figure. ogic iagram MAXIMUM RATINGS Symbol Parameter alue Unit CC C Supply oltage (Referenced to ) 0.5 to +7.0 in C Input oltage (Referenced to ) 0.5 to CC out C Output oltage (Referenced to ) 0.5 to CC I in C Input Current, per Pin ±20 ma I out C Output Current, per Pin ±25 ma I CC C Supply Current, CC and Pins ±50 ma P Power issipation in Still Air, SOIC Package TSSOP Package T stg Storage Temperature 65 to + 50 C ES I atchup ES Withstand oltage uman Body Model (Note ) Machine Model (Note 2) atchup Performance Above and Below at 25 C (Note 3) >2000 >200 mw ±00 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Tested to EIA / JES22 A4 A. 2. Tested to EIA / JES22 A5 A. 3. Tested to EIA / JES78. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or CC ). Unused outputs must be left open. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit CC C Supply oltage (Referenced to ) in, out C Input oltage, Output oltage (Referenced to ) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 2) ns 2

3 MC74CT259A C EECTRICA CARACTERISTICS (oltages Referenced to ) Guaranteed imit Symbol Parameter Test Conditions CC 55 to 25 C 85 C 25 C Unit I Minimum igh evel Input oltage out = 0. or CC 0. I out 20 A I Maximum ow evel Input oltage out = 0. or CC 0. I out 20 A O Minimum igh evel Output oltage in = I or I I out 20 A O I in Maximum ow evel Output oltage Maximum Input eakage Current in = I or I I out 5.2 ma in = I or I I out 20 A in = I or I I out 5.2 ma in = CC or 5.5 ± 0. ±.0 ±.0 A I CC Maximum Quiescent Supply Current (per Package) in = CC or I out = 0 A A I CC Additional Quiescent Supply Current in = 2.4, Any One Input in = CC or, Other Inputs I out = 0 A C 25 to 25 C ma 3

4 MC74CT259A AC EECTRICA CARACTERISTICS ( CC = 4.5 to 5.5, C = 50 pf, Input t r = t f = 6 ns) Symbol t P, t P t P, t P t P, t P t P t T, t T Parameter Maximum Propagation elay, ata to Output (Figures 2 and 7) Maximum Propagation elay, Address Select to Output (Figures 3 and 7) Maximum Propagation elay, Enable to Output (Figures 4 and 7) Maximum Propagation elay, Reset to Output (Figures 5 and 7) Maximum Output Transition Time, Any Output (Figures 2 and 7) Guaranteed imit 55 to 25 C 85 C 25 C Unit ns ns ns ns ns C in Maximum Input Capacitance pf 25 C, CC = 5.0 C P Power issipation Capacitance (Per Package) 30 pf TIMING REQUIREMENTS ( CC = 4.5 to 5.5, Input t r = t f = 6 ns) Symbol t su t h t w Parameter Minimum Setup Time, Address or ata to Enable (Figure 6) Minimum old Time, Enable to Address or ata (Figure 6) Minimum Pulse Width, Reset or Enable (Figure 4 or 5) Guaranteed imit 55 to 25 C 85 C 25 C Unit ns ns ns 4

5 MC74CT259A SWITCING WAEFORMS ATA IN t r t f ATA IN %.3 0% t P t P 90%.3 OUTPUT Q 0% 50% t T t T ARESS SEECT OUTPUT Q t P % t P Figure 2. Figure 3. ATA IN ENABE t w t w t P t P 3.0 CC ATA IN RESET t P.3 t w OUTPUT Q 50% OUTPUT Q 50% Figure 4. Figure 5. TEST POINT ATA IN OR ARESS SEECT ENABE.3 t su.3 t h() t su t h() EICE UNER TEST OUTPUT C * *Includes all probe and jig capacitance Figure 6. Figure 7. Test Circuit 5

6 MC74CT259A ATA INPUT 3 4 Q0 5 Q 6 Q2 7 Q3 A0 ARESS INPUTS A A2 3 TO 8 ECOER 9 Q4 ENABE 4 0 Q5 Q6 2 Q7 RESET 5 Figure 8. Expanded ogic iagram ORERING INFORMATION MC74CT259AG evice Package Shipping SOIC 6 (Pb Free) 48 Units / Rail MC74CT259AR2G SOIC 6 (Pb Free) 2500 Tape & Reel MC74CT259ATR2G TSSOP 6* 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. *This package is inherently Pb Free. 6

7 MC74CT259A PACKAGE IMENSIONS A B SOIC 6 CASE 75B 05 ISSUE K P 8 P 0.25 (0.00) M B S NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: MIIMETER. 3. IMENSIONS A AN B O NOT INCUE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SA BE 0.27 (0.005) TOTA IN EXCESS OF TE IMENSION AT MAXIMUM MATERIA CONITION. T SEATING PANE G 6 P K C M R X 45 J F MIIMETERS INCES IM MIN MAX MIN MAX A B C F G.27 BSC BSC J K M P R (0.00) M T B S A S SOERING FOOTPRINT* 8X X.2 6 6X PITC 8 9 IMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOERRM/. 7

8 MC74CT259A PACKAGE IMENSIONS 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PANE U PIN IENT. U S S 2X /2 C 6X K REF 0.0 (0.004) M T U S S A G B U TSSOP 6 T SUFFIX CASE 948F 0 ISSUE B J N N J F ETAI E ETAI E SOERING FOOTPRINT* 7.06 K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.00) M NOTES:. IMENSIONING AN TOERANCING PER ANSI Y4.5M, CONTROING IMENSION: MIIMETER. 3. IMENSION A OES NOT INCUE MO FAS. PROTRUSIONS OR GATE BURRS. MO FAS OR GATE BURRS SA NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCUE INTEREA FAS OR PROTRUSION. INTEREA FAS OR PROTRUSION SA NOT EXCEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INCUE AMBAR PROTRUSION. AOWABE AMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE K IMENSION AT MAXIMUM MATERIA CONITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PANE W. MIIMETERS INCES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC W J J K K BSC BSC M PITC 6X X.26 IMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOERRM/. 8

9 MC74CT259A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORERING INFORMATION ITERATURE FUFIMENT: iterature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative MC74CT259A/

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