MC74HC373A. Octal 3-State Non-Inverting Transparent Latch. High Performance Silicon Gate CMOS

Transcription

1 Octal 3-State Non-Inverting Traparent Latch High Performance Silicon Gate CMOS The MC74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear traparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high impedance state. Thus, data may be latched even when the outputs are not enabled. The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC373A is the non inverting version of the HC533A. Features Output rive Capability: LSTTL Loads Outputs irectly Interface to CMOS, NMOS and TTL Operating oltage Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS evices In Compliance with the JEEC Standard No. 7.0 A Requirements Chip Complexity: 86 FETs or 46.5 Equivalent Gates These evices are Pb Free and are RoHS Compliant ATA INPUTS LATCH ENAB ENAB LOGIC IAGRAM PIN = PIN 0 = GN NONINERTING S SOIC W SUFFIX CASE 75 SOIC MARKING IAGRAMS HC373A AWLYYWWG PIN ASSIGNMENT ENAB GN TSSOP T SUFFIX CASE 948E LATCH ENAB HC 373A ALYW TSSOP A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNCTION TAB Inputs Output Output Latch Enable Enable L H H H L H L L L L X No Change H X X Z X = on t Care Z = High Impedance ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 4 August, 4 Rev. Publication Order Number: MC74HC373A/

2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ esign Criteria alue Units ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Count* 46.5 ea ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Propagation elay.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Power issipation W ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Speed Power Product *Equivalent to a two input NAN gate. ÎÎÎ pj MC74HC373A MAXIMUM RATINGS Symbol Parameter alue Unit C Supply oltage (Referenced to GN) 0.5 to +7.0 in C Input oltage (Referenced to GN) 0.5 to out C Output oltage (Referenced to GN) 0.5 to I in C Input Current, per Pin ± ma I out C Output Current, per Pin ±35 ma I CC C Supply Current, and GN Pi ±75 ma P Power issipation in Still Air, SOIC Package TSSOP Package 450 mw T stg Storage Temperature 65 to +0 C T L Lead Temperature, mm from Case for 0 Seconds C (SOIC, SSOP or TSSOP Package) 60 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. erating: SOIC Package: 7 mw/ C from 65 to 5 C TSSOP Package: 6. mw/ C from 65 to 5 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit C Supply oltage (Referenced to GN) in, out C Input oltage, Output oltage (Referenced to GN) 0 T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time = (Figure ) = = 0 0 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

3 C ECTRICAL CHARACTERISTICS (oltages Referenced to GN) Symbol Parameter Test Conditio IH IL OH OL Minimum High Level Input oltage Maximum Low Level Input oltage Minimum High Level Output oltage Maximum Low Level Output oltage out = I out A out = I out A in = IH I out A in = IH in = IL I out A in = IL I out.4 ma I out ma I out 7.8 ma I out.4 ma I out ma I out 7.8 ma Guaranteed Limit 55 to 5 C 85 C 5 C Unit I in Maximum Input Leakage Current in = or GN ± ±.0 ±.0 A I OZ Maximum Three State Leakage Current Output in High Impedance State in = IL or IH out = or GN ±0.5 ± ±0 A I CC Maximum uiescent Supply Current (per Package) in = or GN I out = 0 A AC ECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = ) Symbol t PLZ t PHZ t PZL t PZH t TLH t THL Parameter Maximum Propagation elay, Input to (Figures and 5) Maximum Propagation elay, Latch Enable to (Figures and 5) Maximum Propagation elay, Output Enable to (Figures 3 and 6) Maximum Propagation elay, Output Enable to (Figures 3 and 6) Maximum Output Traition Time, Any Output (Figures and 5) A Guaranteed Limit 55 to 5 C 85 C 5 C C in Maximum Input Capacitance pf C out Maximum Three State Output Capacitance pf (Output in High Impedance State) Unit C P Power issipation Capacitance (Per Enabled Output)* * Used to determine the no load dynamic power coumption: P = C P CC f + I CC. 5 C, = 36 pf 3

4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REUIREMENTS (C L = 50 pf, Input t r = t f = ) Symbol Parameter Figure olts t su Minimum Setup Time, Input to Latch Enable 4 t h Minimum Hold Time, Latch Enable to Input 4 t w Minimum Pulse Width, Latch Enable t r, t f Maximum Input Rise and Fall Times Guaranteed Limit 55 to 5 C 85 C 5 C Min Max Min Max Min Max Unit SWITCHING WAEFORMS INPUT t r t TLH 0% 90% 0% 90% t f GN t THL LATCH ENAB t w GN Figure. Figure. ENAB t PZH t PHZ t PZL t PLZ 0% 90%.3 GN HIGH IMPEANCE OL OH HIGH IMPEANCE INPUT LATCH ENAB t su ALI t h GN GN Figure 3. Figure

5 TEST CIRCUITS TEST POINT TEST POINT EICE UNER TEST C L * EICE UNER TEST k C L * CONNECT TO WHEN TESTING t PLZ AN t PZL. CONNECT TO GN WHEN TESTING t PHZ AN t PZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Figure Figure 7. Expanded Logic iagram ORERING INFORMATION MC74HC373AWG MC74HC373AWRG MC74HC373ATG evice Package Shipping SOIC WIE SOIC WIE TSSOP Units / Rail 000 Units / Reel 75 Units / Rail MC74HC373ATRG TSSOP Units / Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR80/. 5

6 PACKAGE IMENSIONS TSSOP T SUFFIX CASE 948E 0 ISSUE C 5 (0.006) T L 5 (0.006) T U X L/ PIN IENT U S S C 00 (0.004) T SEATING PLANE X K REF 0 (0.004) M T U S S 0 A G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SORING FOOTPRINT* 7.06 SECTION N N 0.5 (0.00) M NOTES:. IMENSIONING AN TORANCING PER ANSI YM, 98.. CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERA FLASH OR PROTRUSION. INTERA FLASH OR PROTRUSION SHALL NOT EXCEE 0.5 (0.00) PER SIE. 5. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWAB AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. F MILLIMETERS INCHES IM MIN MAX MIN MAX ETAIL E A B C W F G 0.65 BSC 0.06 BSC H J ETAIL E J K K L 6.40 BSC 0.5 BSC M PITCH 6X X.6 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SORRM/. 6

7 PACKAGE IMENSIONS SOIC W SUFFIX CASE ISSUE G H 0X 0.5 M B M E A h X 45 NOTES:. IMENSIONS ARE IN MILLIMETERS.. INTERPRET IMENSIONS AN TORANCES PER ASME YM, IMENSIONS AN E O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 5 PER SIE. 5. IMENSION B OES NOT INCLUE AMBAR PROTRUSION. ALLOWAB PROTRUSION SHALL BE 3 TOTAL IN EXCESS OF B IMENSION AT MAXIMUM MATERIAL CONITION. X B 0.5 M T A S 8X e 0 B B S A A T SEATING PLANE C L MILLIMETERS IM MIN MAX A A B C E e.7 BSC H h L ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74HC373A/