74LVC374A. Low-Voltage CMOS Octal D-Type Flip-Flop. With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting)

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1 Low-Voltage CMOS Octal -Type Flip-Flop With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting) The 74LVC374A is a high performance, non inverting octal type flip flop operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows 74LVC374A inputs to be safely driven from 5 V devices. The 74LVC374A coists of 8 edge triggered flip flops with individual type inputs and 3 state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flip flops. The eight flip flops will store the state of individual inputs that meet the setup and hold time requirements on the LOW to HIGH Clock () traition. With the OE LOW, the contents of the eight flip flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip flops. Features esigned for 1.2 to 3.6 V V CC Operation 5 V Tolerant Interface Capability With 5 V TTL Logic Supports Live Iertion and Withdrawal I OFF Specification Guarantees High Impedance When V CC = 0 V 24 ma Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 A) Substantially Reduces System Power Requirements ES Performance: Human Body Model >2000 V Machine Model >200 V These are Pb Free evices 20 1 TSSOP 20 T SUFFIX CASE 948E MARKING IAGRAM ORERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. 20 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package 1 LVC 374A ALYW (Note: Microdot may be in either location) Semiconductor Components Industries, LLC, 2016 April, 2016 Rev. 2 1 Publication Order Number: 74LVC374A/

2 OE 1 11 V CC O7 7 6 O6 O5 5 4 O O O O2 OE O0 0 1 O1 O2 2 3 O3 GN Figure 1. Pinout: 20 Lead (Top View) O O4 PIN NAMES Pi OE Function Output Enable Input O5 0 7 O0 O7 Clock Pulse Input ata Inputs 3 State Outputs O O7 Figure 2. LOGIC IAGRAM TRUTH TABLE INPUTS OUTPUTS OE n On OPERATING MOE L L l h L H Load and Read Register L X NC Hold and Read Register H X Z Hold and isable Outputs H H l h H = High Voltage Level h = High Voltage Level One Setup Time Prior to the Low to High Clock Traition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Low to High Clock Traition NC = No Change, State Prior to Low to High Clock Traition X = High or Low Voltage Level and Traitio are Acceptable Z = High Impedance State = Low to High Traition = Not a Low to High Traition; For I CC Reaso, O NOT FLOAT Inputs Z Z Load Internal Register and isable Outputs 2

3 MAXIMUM RATINGS Symbol Parameter Condition Value Unit VCC C Supply Voltage 0.5 to +6.5 V V I C Input Voltage 0.5 V I +6.5 V V O C Output Voltage Output in 3 State 0.5 V O +6.5 V Output in HIGH or LOW State (Note 1) 0.5 V O V CC V IIK C Input iode Current V I < GN 50 ma IOK C Output iode Current V O < GN 50 ma V O > V CC +50 ma I O C Output Source/Sink Current ±50 ma ICC C Supply Current Per Supply Pin ±100 ma IGN C Ground Current Per Ground Pin ±100 ma TSTG Storage Temperature Range 65 to +150 C T L Lead Temperature, 1 mm from Case for 10 Seconds T L = 260 C T J Junction Temperature Under Bias T J = 135 C JA Thermal Resistance (Note 2) TSSOP C/W MSL Moisture Seitivity Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. I O absolute maximum rating must be observed. 2. Measured with minimum pad spacing on an FR4 board, using 10 mm by 1 inch, 2 ounce copper trace no air flow. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Typ Max Unit V CC Supply Voltage Operating Functional V V I Input Voltage V V O Output Voltage HIGH or LOW State 3 State 0 0 V CC 5.5 V I OH HIGH Level Output Current V CC = 3.0 V 3.6 V V CC = 2.7 V 3.0 V ma I OL LOW Level Output Current V CC = 3.0 V 3.6 V V CC = 2.7 V 3.0 V ma T A Operating Free Air Temperature C t/ V Input Traition Rise or Fall Rate, V CC = 1.65 to 2.7 V V CC = 2.7 to 3.6 V /V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3

4 C ELECTRICAL CHARACTERISTICS 40 to +85 C 40 to +125 C Symbol Parameter Conditio Min Typ (Note 3) Max Min Typ (Note 3) Max Unit V IH HIGH level input voltage V CC = 1.2 V V V CC = 1.65 V to 1.95 V 0.65 x 0.65 x V CC V CC V CC = 2.3 V to 2.7 V V CC = 2.7 V to 3.6 V V IL LOW level input voltage V CC = 1.2 V V V CC = 1.65 V to 1.95 V 0.35 x V CC 0.35 x V CC V CC = 2.3 V to 2.7 V V CC = 2.7 V to 3.6 V V OH HIGH level output voltage V I = V IH or V IL V I O = 100 A; V CC = 1.65 V to 3.6 V V CC 0.2 V CC 0.3 I O = 4 ma; V CC = 1.65 V I O = 8 ma; V CC = 2.3 V I O = 12 ma; V CC = 2.7 V I O = 18 ma; V CC = 3.0 V I O = 24 ma; V CC = 3.0 V V OL LOW level output voltage V I = V IH or V IL V I O = 100 A; V CC = 1.65 V to 3.6 V I O = 4 ma; V CC = 1.65 V I O = 8 ma; V CC = 2.3 V I O = 12 ma; V CC = 2.7 V I O = 24 ma; V CC = 3.0 V I I Input leakage current V I = 5.5 V or GN; V CC = 3.6 V I OZ OFF state output current VI = VIH or VIL; V O = 5.5 V or GN; V CC = 3.6 V ±0.1 ±5 ±0.1 ±20 A ±0.1 ±5 ±0.1 ±20 A I OFF Power off leakage current V I or V O = 5.5 V; V CC = 0.0 V ±0.1 ±10 ±0.1 ±20 A I CC Supply current V I = V CC or GN; I O = 0 A; V CC = 3.6 V A I CC Additional supply current per input pin; V I = V CC 0.6 V; I O = 0 A; V CC = 2.7 V to 3.6 V A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio. 3. All typical values are measured at T A = 25 C and V CC = 3.3 V, unless stated otherwise. 4

5 AC ELECTRICAL CHARACTERISTICS (t R = t F = 2.5 ) Symbol Parameter Conditio tpd Propagation elay (Note 5) to On Min 40 to +85 C Typ (Note 4) Max Min 40 to +125 C Typ (Note 4) V CC = 1.2 V 16.0 Max V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V Unit ten Enable Time (Note 6) OE to On tdis isable Time (Note 7) OE to On tw tsu th Pulse Width HIGH or LOW Set up Time n to Hold Time n to V CC = 1.2 V 19.0 V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V V CC = 1.2 V 8.0 V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V fmax Maximum Frequency V CC = 1.65 V to 1.95 V V CC = 2.3 V to 2.7 V V CC = 2.7 V V CC = 3.0 V to 3.6 V MHz tsk(0) Output Skew Time (Note 8) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio. 4. Typical values are measured at TA = 25 C and VCC = 3.3 V, unless stated otherwise. 5. t pd is the same as t PLH and t PHL. 6. t en is the same as t PZL and t PZH. 7. t dis is the same as t PLZ and t PHZ. 8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 5

6 YNAMIC SWITCHING CHARACTERISTICS Symbol Characteristic Condition T A = +25 C Min Typ Max Unit V OLP ynamic LOW Peak Voltage (Note 9) V CC = 3.3 V, C L = 50 pf, V IH = 3.3 V, V IL = 0 V V CC = 2.5 V, C L = 30 pf, V IH = 2.5 V, V IL = 0 V V V OLV ynamic LOW Valley Voltage (Note 9) V CC = 3.3 V, C L = 50 pf, V IH = 3.3 V, V IL = 0 V V CC = 2.5 V, C L = 30 pf, V IH = 2.5 V, V IL = 0 V 9. Number of outputs defined as n. Measured with n 1 outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state V CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit C IN Input Capacitance V CC = 3.3 V, V I = 0 V or V CC 5.0 pf C OUT Output Capacitance V CC = 3.3 V, V I = 0 V or V CC 6.0 pf C P Power issipation Capacitance (Note 10) 10. is used to determine the dynamic power dissipation (P in W). P C P V 2 CC fi N CL V 2 CC fo where: fi = input frequency in MHz; fo = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in Volts N = number of outputs switching (C L x V 2 CC x fo) = sum of the outputs Per flip flop; V I = GN or V CC V CC = 1.65 V to 1.95 V 11.6 V CC = 2.3 V to 2.7 V 13.6 V CC = 3.0 V to 3.6 V 15.4 pf 6

7 n t s t h f max t PLH, t PHL 2.7 V 0 V 2.7 V 0V OE On t PZH t PZL 1.5V t PHZ t PLZ 2.7 V 0 V V CC V OH V 0 V 3.0 V On V OH On 1.5V V OL V V OL GN WAVEFORM 1 PROPAGATION ELAYS, SETUP AN HOL TIMES t R = t F = 2.5, 10% to 90%; f = 1 MHz; t W = 500 WAVEFORM 2 OUTPUT ENABLE AN ISABLE TIMES t R = t F = 2.5, 10% to 90%; f = 1 MHz; t W = V t w 0 V t w 2.7 V 0 V WAVEFORM 3 PULSE WITH t R = t F = 2.5 (or fast as required) from 10% to 90%; Output requirements: V OL 0.8 V, V OH 2.0 V VCC Symbol 3.3 V ± 0.3 V 2.7 V V CC < 2.7 V Vmi V CC /2 Vmo V CC /2 VHZ V OL V V OL V V OL V VLZ V OH 0.3 V V OH 0.3 V V OH 015 V Figure 3. AC Waveforms 7

8 V CC PULSE GENERATOR UT R 1 6 V OPEN GN R T C L R L Supply Voltage Input Load VEXT V CC (V) V I t r, t f C L R L tplh, tphl tplz, tpzl tphz, tpzh 1.2 VCC 2 30 pf 1 k Open 2 x V CC GN VCC 2 30 pf 1 k Open 2 x V CC GN VCC 2 30 pf 500 Open 2 x V CC GN V pf 500 Open 2 x V CC GN V pf 500 Open 2 x V CC GN Figure 4. Test Circuit ORERING INFORMATION evice Package Shipping 74LVC374ATR2G TSSOP 20 (Pb Free) 2500 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR8011/. 8

9 PACKAGE IMENSIONS TSSOP 20 T SUFFIX CASE 948E 02 ISSUE C 0.15 (0.006) T L 0.15 (0.006) T U 2X L/2 PIN 1 IENT U S S C (0.004) T SEATING PLANE 20X K REF 0.10 (0.004) M T U S V S A V G H B U J J1 N N K K1 ÍÍÍÍ ÍÍÍÍ SECTION N N F ETAIL E 0.25 (0.010) ETAIL E SOLERING FOOTPRINT* M W NOTES: 1. IMENSIONING AN TOLERANCING PER ANSI Y14.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.15 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.010) PER SIE. 5. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M PITCH 16X X 1.26 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. 9

10 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor E. 32nd Pkwy, Aurora, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative 74LVC374A/