74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS

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1 of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC38 decodes a three bit Address to one of eight active low outputs. This device features three Chip Select inputs, two active low and one active high to facilitate the demultiplexing, cascading, and chip selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: to V Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM 2000 V; Machine Model 200 V Chip Complexity: 00 FETs or 29 Equivalent Gates These are Pb Free Devices 6 6 SOIC 6 D SUFFIX CASE 75B TSSOP 6 DT SUFFIX CASE 948F 6 MARKING DIAGRAMS HC38G AWLYWW 6 HC 38 ALYW HC38 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 2007 March, 2007 Rev. Publication Order Number: 74HC38/D

2 A0 A A Y0 Y CS2 4 3 Y2 CS3 5 2 Y3 CS Y Y4 Y5 GND 8 9 Y6 Figure. Pin Assignment ADDRESS INPUTS A0 A A2 6 CS CHIP 4 SELECT CS2 INPUTS 5 CS Y0 Y Y2 Y3 Y4 Y5 9 7 Y6 Y7 PIN 6 = PIN 8 = GND Figure 2. Logic Diagram ACTIVE LOW OUTPUTS FUNCTION TABLE Inputs Outputs CSCS2 CS3 A2 A A0 Y0 Y Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = high level (steady state); L = low level (steady state); X = don t care ORDERING INFORMATION 74HC38DR2G Device Package Shipping SOIC 6 (Pb Free) 2500 / Tape & Reel 74HC38DTR2G TSSOP 6* 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit DC Supply Voltage (Referenced to GND) 0.5 to V V in DC Input Voltage (Referenced to GND) 0.5 to V V out DC Output Voltage (Referenced to GND) 0.5 to V I in DC Input Current, per Pin ±20 ma I out DC Output Current, per Pin ±25 ma I CC DC Supply Current, and GND Pins ±50 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds (SOIC or TSSOP Package) 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6..W/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). mw C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GND (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply Voltage (Referenced to GND) V V in, V out DC Input Voltage, Output Voltage (Referenced to GND) 0 V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time = V (Figure 2) = V = V ns 3

4 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions V IH V IL V OH V OL I in I CC Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) V out = V or V I out 20 A V out = V or V I out 20 A V in = V IH or V IL I out 20 A V in = V IH or V IL I out 2.4 ma I out 4.0 ma I out 5.2 ma V in = V IH or V IL I out 20 A V in = V IH or V IL I out 2.4 ma I out 4.0 ma I out 5.2 ma (V) Guaranteed Limit 55 C to 25 C 85 C 25 C V in = or GND ± ±.0 ±.0 A V in = or GND I out = 0 A Unit V A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = ns) Symbol t PLH, t PLH, t PLH, t TLH, t THL Parameter Maximum Propagation Delay, Input A to Output Y (Figures and 4) Maximum Propagation Delay, CS to Output Y (Figures 2 and 4) Maximum Propagation Delay, CS2 or CS3 to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 2 and 4) (V) Guaranteed Limit 55 C to 25 C 85 C 25 C C in Maximum Input Capacitance pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D) C, = 5.0 V C PD Power Dissipation Capacitance (Per Package)* 55 pf * Used to determine the no load dynamic power consumption: P D = C PD V 2 CC f + I CC. For load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D) V V V Unit ns ns ns ns 4

5 SWITCHING WAVEFORMS VALID INPUT A 50% t PLH OUTPUT Y 50% VALID GND INPUT CS OUTPUT Y t r 90% 50% 0% 90% 50% 0% t f t PLH GND t THL t TLH Figure. Figure 2. TEST POINT INPUT CS2, CS3 OUTPUT Y 90% 50% 0% t f 90% 50% 0% t r t PLH GND DEVICE UNDER TEST OUTPUT C L * t THL Figure 3. t TLH *Includes all probe and jig capacitance Figure 4. Test Circuit PIN DESCRIPTIONS ADDRESS INPUTS A0, A, A2 (Pins, 2, 3) Address inputs. These inputs, when the chip is selected, determine which of the eight outputs is active low. CONTROL INPUTS CS, CS2, CS3 (Pins 6, 4, 5) Chip select inputs. For CS at a high level and CS2, CS3 at a low level, the chip is selected and the outputs follow the Address inputs. For any other combination of CS, CS2, and CS3, the outputs are at a logic high. OUTPUTS Y0 Y7 (Pins 5, 4, 3, 2,, 0, 9, 7) Active low Decoded outputs. These outputs assume a low level when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not selected. 5

6 EXPANDED LOGIC DIAGRAM 5 Y0 4 Y A0 3 Y2 A 2 2 Y3 A2 3 Y4 CS3 CS Y5 Y6 7 Y7 CS 6 6

7 PACKAGE DIMENSIONS SOIC 6 CASE 75B 05 ISSUE K A B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G D 6 PL K C M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R (0.00) M T B S A S SOLDERING FOOTPRINT* 8X X.2 6 6X PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 PACKAGE DIMENSIONS TSSOP 6 CASE 948F 0 ISSUE B 5 (0.006) T 5 (0.006) T 0 (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C 6X K REF 0 (0.004) M T U S V S A V G B U H J N N J F DETAIL E DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.00) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 6X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8

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