74FST Bit Bus Switch
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1 4FST32 4 Bit Bus Switch The ON Semiconductor 4FST32 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and. Volts. The device exhibits extremely low R ON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. The device consists of four independent bit switches with separate Output/Enable (OE) pins. Port A is connected to Port B when OE is low. If OE is high, the switch is high Z. Features R ON 4 Typical Less Than 0.2 ns Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin For Pin Compatible With QS32, FST32, CBT32 All Popular Packages: QSOP 6, TSSOP 4, SOIC 4 All Devices in Package TSSOP are Inherently Pb Free* OE A B OE 2 2A 2B NC OE A B OE 2 2A 2B V CC OE 4 4A 4B OE 3 3A 3B Figure. Pin Assignment for SOIC and TSSOP V CC OE 4 4A 4B OE 3 3A 3B NC Figure 2. Pin Assignment for QSOP 4 SOIC 4 D SUFFIX CASE A 4 TSSOP 4 DT SUFFIX CASE 948G 6 QSOP 6 QS SUFFIX CASE 492 FST32 AWLYWW FST 32 ALYW A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week PIN NAMES Pin Description OE, OE 2, OE 3, OE 4 Bus Switch Enables A, 2A, 3A, 4A Bus A B, 2B, 3B, 4B Bus B NC Not Connected 4 MARKING DIAGRAMS S32 ALYW ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 4 6 *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2006 June, 2006 Rev. 3 Publication Order Number: 4FST32/D
2 4FST32 OE A 2 3 B OE 2 4 2A 6 2B OE 3 0 3A 9 8 3B OE 4 3 4A 2 4B Figure 3. Logic Diagram TRUTH TABLE Inputs OE L H Outputs A, B A = B Z ORDERING INFORMATION Device Order Number Package Shipping 4FST32D SOIC 4 Units / Rail 4FST32DR2 SOIC Units / Tape & Reel 4FST32DT TSSOP* (Pb Free) 96 Units / Rail 4FST32DTR2 TSSOP* (Pb Free) 200 Units / Tape & Reel 4FST32QS QSOP 6 96 Units / Rail 4FST32QSR QSOP Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2
3 4FST32 MAXIMUM RATINGS Symbol Parameter Value Unit V CC DC Supply Voltage 0. to.0 V V I DC Input Voltage 0. to.0 V V O DC Output Voltage 0. to.0 V I IK DC Input Diode Current V I 0 ma I OK DC Output Diode Current V O 0 ma I O DC Output Sink Current 28 ma I CC DC Supply Current per Supply Pin 00 ma I DC Ground Current per Ground Pin 00 ma T STG Storage Temperature Range 6 to 0 C T L Lead Temperature, mm from Case for 0 Seconds 260 C T J Junction Temperature Under Bias 0 C JA Thermal Resistance (Note ) SOIC TSSOP QSOP MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0.2 in V ESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) I Latchup Latchup Performance Above V CC and Below at 8 C (Note 4) 00 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Measured with minimum pad spacing on an FR4 board, using 0 mm by inch, 2 ounce copper trace with no air flow. 2. Tested to EIA/JESD22 A4 A. 3. Tested to EIA/JESD22 A A. 4. Tested to EIA/JESD8. C/W V RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC Supply Voltage Operating, Data Retention Only 4.0. V V I Input Voltage (Note ) 0. V V O Output Voltage (HIGH or LOW State) 0 V CC V T A Operating Free Air Temperature 40 8 C t/ V Input Transition Rise or Fall Rate Switch Control Input Switch I/O. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. 0 0 DC ns/v 3
4 4FST32 DC ELECTRICAL CHARACTERISTICS V CC T A = 40 C to 8 C Symbol Parameter Conditions (V) Min Typ* Max Unit V IK Clamp Diode Resistance I IN = 8mA 4..2 V V IH High Level Input Voltage 4.0 to. 2.0 V V IL Low Level Input Voltage 4.0 to. 0.8 V I I Input Leakage Current 0 V IN. V..0 A I OZ OFF STATE Leakage Current 0 A, B V CC..0 A R ON Switch On Resistance (Note 6) V IN = 0 V, I IN = 64 ma 4. 4 V IN = 0 V, I IN = 30 ma 4. 4 V IN = 2.4 V, I IN = ma 4. 8 V IN = 2.4 V, I IN = ma I CC Quiescent Supply Current V IN = V CC or, I OUT = 0. 3 A I CC Increase In I CC per Input One input at 3.4 V, Other inputs at V CC or. 2. ma *Typical values are at V CC =.0 V and T A = 2 C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. AC ELECTRICAL CHARACTERISTICS Limits T A = 40 C to 8 C V CC = 4. to. V V CC = 4.0 V Symbol Parameter Conditions Figures Min Max Min Max Unit t PHL, t PLH Prop Delay Bus to Bus (Note ) V I = OPEN 4 and ns t PZH, Output Enable Time V I = V for t PZL 4 and.0.0. ns t PZL V I = OPEN for t PZH t PHZ, Output Disable Time V I = V for t PLZ 4 and..3.6 ns t PLZ V I = OPEN for t PHZ. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 0 pf load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit C IN Control Pin Input Capacitance V CC =.0 V 3 pf C I/O Input/Output Capacitance V CC, OE =.0 V pf 8. T A = 2 C, f = MHz, Capacitance is characterized but not tested. 4
5 4FST32 AC Loading and Waveforms V I FROM UNDER TEST C L * Input driven by 0 source terminated in CL includes load and stray capacitance. *C L = 0 pf Figure 4. AC Test Circuit SWITCH INPUT 3.0 V 90 % 90 %. V. V Vmi 0 % 0 % t PLH t PLH V OH. V. V V OL Figure. Propagation Delays ENABLE INPUT 90 %. V 3.0 V 90 %. V 0 % 0 % t PZL t PZL t PZH. V. V V OL V V OL t PHZL V OH V OH 0.3 V Figure 6. Enable/Disable Delays
6 4FST32 PACKAGE DIMENSIONS SOIC 4 D SUFFIX CASE A 03 ISSUE G T SEATING PLANE G A 4 8 D 4 PL B K P PL C 0.2 (0.00) M T B S A S 0.2 (0.00) M B M R X 4 M J F. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.00) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.2 BSC 0.00 BSC J K M 0 0 P R TSSOP 4 DT SUFFIX CASE 948G 0 ISSUE O 0. (0.006) T 0. (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S V S N (0.00) M B U A V G H N J J F K K ÇÇÇ ÉÉ ÇÇÇ ÉÉ SECTION N N W. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0. (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.2 (0.00) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.6 BSC BSC H J J K K L 6.40 BSC 0.22 BSC M
7 4FST32 PACKAGE DIMENSIONS QSOP 6 QS SUFFIX CASE ISSUE O L B 0.2 (0.00) M T C A G R U K P Q H x 4 RAD X 0.00 DP. MAX RAD TYP V MOLD PIN MARK N 8 PL. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE.. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES MILLIMETERS DIM MAX MIN MAX MIN A B C D F G 0.02 BSC 0.64 BSC H J K L M N 0 0 P Q DIA 0. DIA R U V D 6 PL 0.2 (0.00) M T B S A S T SEATING PLANE M J F ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 802 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative 4FST32/D
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74VHC08 Quad 2-Input AND Gate Features High Speed: t PD = 4.3ns (Typ.) at T A = 25 C High noise immunity: V NIH = V NIL = 28% V CC (Min.) Power down protection is provided on all inputs Low power dissipation:
NTF3055L175. Power MOSFET 2.0 A, 60 V, Logic Level. N Channel SOT AMPERES, 60 VOLTS R DS(on) = 175 m
NTF355L75 Power MOSFET. A, 6 V, Logic Level NChannel SOT3 Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features
74HCT32. Quad 2 Input OR Gate with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
Quad 2 Input OR Gate with STT Compatible Inputs igh Performance Silicon Gate CMOS The 74CT32 is identical in pinout to the S32. The device has TT compatible inputs. Features Output Drive Capability: 0
MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
Dual D Type Positive Edge Triggered Flip Flop The MC74AC74/74ACT74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred
SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY
uad Flip Flop The LSTTL/MSI SN74LS75 is a high speed uad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored
NL27WZ14. Dual Schmitt Trigger Inverter
N7WZ Dual Schmitt Trigger Inverter The N7WZ is a high performance dual inverter with Schmitt Trigger inputs operating from a.5 to supply. Pin configuration and function are the same as the N7WZ0, but the
74AC00, 74ACT00 Quad 2-Input NAND Gate
74AC00, 74ACT00 Quad 2-Input NAND Gate Features I CC reduced by 50% Outputs source/sink 24mA ACT00 has TTL-compatible inputs Ordering Information Order Number Package Number General Description The AC00/ACT00
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
MC74AC259, MC74ACT Bit Addressable Latch
8-Bit Addressable Latch The MC259/T259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing single
MC74LCX138MEL. With 5 V Tolerant Inputs
With 5 V Tolerant Inputs The MC74LCX38 is a high performance, 3 to 8 decoder/demultiplexer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading
MMBFJ309L, MMBFJ310L, SMMBFJ309L, SMMBFJ310L. JFET - VHF/UHF Amplifier Transistor. N Channel
MMBFJ9L, MMBFJL, SMMBFJ9L, SMMBFJL JFET - VHF/UHF Amplifier Transistor NChannel Features Drain and Source are Interchangeable S Prefix for Automotive and Other Applications Requiring Unique Site and Control
SN74LS157MEL LOW POWER SCHOTTKY
The LSTTL/MSI SN74LS157 is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected
MC74HC138A. 1-of-8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC38A -of-8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC38A is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing
74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs Features 5V tolerant inputs 2.3V 3.6V V CC specifications provided 5.5ns t PD max. (V CC = 3.3V), 10µA I CC max. Power down high impedance
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS22 has an internal
NCS1002A. Constant Voltage / Constant Current Secondary Side Controller
NCS00A Constant Voltage / Constant Current Secondary Side Controller Description The NCS00A is a performance upgrade from the NCS00 focused on reducing power consumption in applications that require more
NL17SZ16. Single Input Buffer
NL7SZ6 Single Input Buffer The NL7SZ6 is a single input Buffer in two tiny footprint packages. The device performs much as LCX multi gate products in speed and drive. Features Tiny SOT 33 and SOT 3 Packages
MMBT5550L, MMBT5551L, SMMBT5551L. High Voltage Transistors. NPN Silicon
MMBT55L, MMBT555L, SMMBT555L High Voltage Transistors NPN Silicon Features AECQ Qualified and PPAP Capable S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements
2N5401. PNP Silicon. These are Pb Free Devices* Features. MAXIMUM RATINGS THERMAL CHARACTERISTICS MARKING DIAGRAM
Preferred Device Amplifier Transistors PNP Silicon Features These are PbFree Devices* MAXIMUM RATINGS Rating Symbol alue Unit Collector Emitter oltage CEO 1 Collector Base oltage CBO 16 Emitter Base oltage
NTMFS4833NT3G. Power MOSFET. 30 V, 191 A, Single N-Channel, SO-8 FL Features
Power MOSFET 3 V, 191 A, Single N-Channel, SO-8 FL Features Low R S(on) to Minimize Conduction Losses Low Capacitance to Minimize river Losses Optimized Gate Charge to Minimize Switching Losses These are
MC74LVX32. Quad 2-Input OR Gate. With 5 V Tolerant Inputs
MC4X32 Quad 2-Input OR Gate With 5 Tolerant Inputs The MC4X32 is an advanced high speed CMOS 2 input OR gate. The inputs tolerate voltages up to.0, allowing the interface of 5.0 systems to 3.0 systems.
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
NL27WZ00. Dual 2 Input NAND Gate L1 D
Dual 2 Input NAND Gate The N27WZ00 is a high performance dual 2 input NAND Gate operating from a to 5.5 supply. Extremely igh Speed: t PD 2.4 ns (typical) at CC = 5 Designed for to 5.5 CC Operation Over
NTF6P02T3. Power MOSFET -6.0 Amps, -20 Volts. P-Channel SOT AMPERES -20 VOLTS R DS(on) = 44 m (Typ.)
NTFPT Power MOSFET. Amps, Volts PChannel SOT Features Low R DS(on) Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified PbFree Package is Available Typical Applications
NGTB20N120IHRWG. 20 A, 1200 V V CEsat = 2.10 V E off = 0.45 mj
NGTB2N2IHRWG IGBT with Monolithic Free Wheeling Diode This Insulated Gate Bipolar Transistor (IGBT) features a robust and cost effective Field Stop (FS) Trench construction, provides and superior performance
NGTB40N135IHRWG. 40 A, 1350 V V CEsat = 2.40 V E off = 1.30 mj
NGTB4N3IHRWG IGBT with Monolithic Free Wheeling Diode This Insulated Gate Bipolar Transistor (IGBT) features a robust and cost effective Field Stop (FS) Trench construction, and provides superior performance
MUR405, MUR410, MUR415, MUR420, MUR440, MUR460
4, 4, 41, 42, 44, 46 42 and 46 are Preferred Devices SWITCHMODE Power Rectifiers These state of the art devices are a series designed for use in switching power supplies, inverters and as free wheeling
NL17SZ125. Non-Inverting 3-State Buffer. The NL17SZ125 is a high performance non inverting buffer operating from a 1.65 V to 5.5 V supply.
Non-Inverting 3-State Buffer The N17SZ125 is a high performance non inverting buffer operating from a 1.65 to 5.5 supply. Features Extremely High Speed: t PD 2.6 ns (typical) at CC = 5.0 Designed for 1.65
BC846, BC847, BC848 Series. General Purpose Transistors. NPN Silicon
BC846, BC847, BC848 Series General Purpose Transistors NPN Silicon These transistors are designed for general purpose amplifier applications. They are housed in the SC7/SOT2 which is designed for low power
NL17SHT08. 2-Input AND Gate / CMOS Logic Level Shifter
N7ST08 -Input AND Gate / CMOS ogic evel Shifter The N7ST08 is an advanced high speed CMOS input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
BC337, BC337-25, BC Amplifier Transistors. NPN Silicon. These are Pb Free Devices. Features MAXIMUM RATINGS
BC337, BC337-25, BC337-4 Amplifier Transistors NPN Silicon Features These are PbFree Devices COLLECTOR MAXIMUM RATINGS Rating Symbol alue Unit 2 BASE Collector Emitter oltage CEO 45 dc Collector Base oltage
2N3903, 2N3904. NPN Silicon. Pb Free Packages are Available* Features. MAXIMUM RATINGS. THERMAL CHARACTERISTICS (Note 1)
N393, N393 is a Preferred Device General Purpose Transistors NPN Silicon Features PbFree Packages are Available* MAXIMUM RATINGS Rating Symbol Value Unit Collector Emitter Voltage V CEO 4 Vdc Collector
NL27WZU04. Dual Unbuffered Inverter
Dual Unbuffered Inverter The N27WZU04 is a high performance dual unbuffered inverter operating from a.5 to 5.5 V supply. These devices are well suited for use as oscillators, pulse shapers, and in many
NL27WZ00. Dual 2-Input NAND Gate. The NL27WZ00 is a high performance dual 2 input NAND Gate operating from a 1.65 V to 5.5 V supply.
Dual 2-Input NAND Gate The N27WZ00 is a high performance dual 2 input NAND Gate operating from a.65 to 5.5 supply. Features Extremely igh Speed: t PD ns (typical) at = 5.0 Designed for.65 to 5.5 Operation
Schmitt Trigger Inputs Outputs Source/Sink 24 ma ACT132 Has TTL Compatible Inputs. ORDERING INFORMATION
The MC74AC/74ACT132 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free output signals. In addition, they have greater noise
MC74VHC1GT50 Noninverting Buffer / CMOS Logic Level Shifter
MC74CGT0 Noninverting Buffer / CMOS Logic Level Shifter TTL Compatible Inputs The MC74CGT0 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation
MC3346. General Purpose Transistor Array One Differentially Connected Pair and Three Isolated Transistor Arrays
General Purpose Transistor Array One Differentially Connected Pair and Three Isolated Transistor Arrays The MC336 is designed for general purpose, low power applications for consumer and industrial designs.
74HC32. Quad 2 Input OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input OR Gate igh Performance Silicon Gate CMOS The is identical in pinout to the S32. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with