MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
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1 Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3 state memory address drivers, clock drivers, and other bus oriented systems. The device has noninverting outputs and two active low output enables. The HC244A is similar in function to the HC240A. Features Output Drive Capability: 5 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: 2.0 to 6.0 Low Input Current: A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 36 FETs or 34 Equivalent Gates Pb Free Packages are Available* PDIP N SUFFIX CASE 738 SOIC DW SUFFIX CASE 75D TSSOP DT SUFFIX CASE 948E MARKING DIAGRAMS MC74HC244AN AWLYYWWG 74HC244A AWLYYWWG HC 244A ALYW SOEIAJ F SUFFIX CASE HC244A AWLYWWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb Free Package = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 05 July, 05 Rev. 0 Publication Order Number: MC74HC244A/D
2 PIN ASSIGNMENT LOGIC DIAGRAM ENABLE A CC A 2 8 YA A YB ENABLE B YA A2 4 6 YA2 A2 4 YB3 5 A3 6 YB2 7 A B4 YA2 B3 YA3 B2 DATA INPUTS A3 A4 B YA3 YA4 YB NONINERTING OUTPUTS YB GND YA4 B B2 B YB2 YB3 FUNCTION TABLE Inputs Outputs Enable A, Enable B A, B YA, YB L L L L H H H X Z Z = high impedance OUTPUT ENABLES B4 7 ENABLE A ENABLE B 9 3 YB4 PIN = CC PIN 0 = GND ORDERING INFORMATION Device Package Shipping MC74HC244AN PDIP 8 Units / Rail MC74HC244ANG PDIP (Pb Free) 8 Units / Rail MC74HC244ADW SOIC WIDE 38 Units / Rail MC74HC244ADWG SOIC WIDE (Pb Free) 38 Units / Rail MC74HC244ADWR2 SOIC WIDE 000 Tape & Reel MC74HC244ADWR2G SOIC WIDE (Pb Free) 000 Tape & Reel MC74HC244ADT TSSOP * 75 Units / Rail MC74HC244ADTG TSSOP * 75 Units / Rail MC74HC244ADTR2 TSSOP * 2500 Tape & Reel MC74HC244ADTR2G TSSOP * 2500 Tape & Reel MC74HC244AF SOEIAJ 40 Units / Rail MC74HC244AFG SOEIAJ (Pb Free) 40 Units / Rail MC74HC244AFEL SOEIAJ 00 Tape & Reel MC74HC244AFELG SOEIAJ (Pb Free) 00 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2
3 MAXIMUM RATINGS Symbol Parameter Î alue Unit CC DC Supply oltage (Referenced to GND) Î 0.5 to in DC Input oltage (Referenced to GND) Î 0.5 to CC out DC Output oltage (Referenced to GND) Î 0.5 to CC I in DC Input Current, per Pin Î ± ma I out DC Output Current, per Pin Î ± 35 ma I CC DC Supply Current, CC and GND Pins Î ± 75 ma P D Power Dissipation in Still Air, Plastic DIP Î 750 mw SOIC Package 500 TSSOP Package 450 T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds Î (Plastic DIP, SOIC, SSOP or TSSOP Package) Î 260 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating Plastic DIP: 0 mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit Î CC DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time CC = ns (Figure ) CC = Î CC = DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. Î Guaranteed Limit Symbol Parameter Î Test Conditions CC 55 to Î 25 C 85 C 25 C Unit IH Minimum High Level Input oltage Î Î out = CC I Î out A Î IL Î Î Maximum Low Level Input oltage Î out = I out A OH Minimum High Level Output Î in = IH Î oltage Î I out A Î in = IH I out 2.4 Î I out 6.0 ma I out 7.8 ma Î OL Maximum Low Level Output oltage Î in = IL I out A Î in = IL I out 2.4 ma I out 6.0 ma Î I out 7.8 ma
4 DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Guaranteed Limit CC 55 to Î Symbol Parameter Test Conditions 25 C 85 C 25 C Unit I in Maximum Input Leakage Current in = CC or GND 6.0 Î ± 0. ±.0 ±.0 A I OZ Maximum Three State Leakage Î Output in High Impedance State Î Current Î in = IL or IH 6.0 ± 0.5 ± 5.0 ± 0 A out = CC or GND I CC Maximum Quiescent Supply Î in = CC or GND Î Current (per Package) Î I out = 0 A A NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6 ns) Guaranteed Limit CC 55 to Symbol Parameter 25 C 85 C 25 C Unit Î t PLH, Maximum Propagation Delay, A to YA or B to YB ns t PHL (Figures and 3) Î t PLZ, Maximum Propagation Delay, Output Enable to YA or YB ns t PHZ (Figures 2 and 4) Î t PZL, Maximum Propagation Delay, Output Enable to YA or YB ns t PZH (Figures 2 and 4) Î t TLH, Maximum Output Transition Time, Any Output ns t THL (Figures and 3) Î C in Maximum Input Capacitance Î pf C out Maximum Three State Output Capacitance Î (Output in High Impedance State) Î Î pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 25 C, CC = 5.0 C PD Power Dissipation Capacitance (Per Buffer)* 34 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 CC f + I CC CC. For load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 4
5 SWITCHING WAEFORMS DATA INPUT A OR B OUTPUT YA OR YB t r t PLH t TLH 0% 50% 90% 0% 50% 90% t f CC GND t PHL t THL ENABLE A OR B OUTPUT Y OUTPUT Y 50% t PZL 50% t PZH 50% t PLZ t PHZ 0% 90% CC GND HIGH IMPEDANCE OL OH HIGH IMPEDANCE Figure. Figure 2. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C L * DEICE UNDER TEST OUTPUT k C L * CONNECT TO CC WHEN TESTING t PLZ AND t PZL. CONNECT TO GND WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit PIN DESCRIPTIONS INPUTS A, A2, A3, A4, B, B2, B3, B4 (Pins 2, 4, 6, 8,, 3, 5, 7) Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled. CONTROLS Enable A, Enable B (Pins, 9) Output enables (active low). When a low level is applied to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state. OUTPUTS YA, YA2, YA3, YA4, YB, YB2, YB3, YB4 (Pins 8, 6, 4, 2, 9, 7, 5, 3) Device outputs. Depending upon the state of the output enable pins, these outputs are either noninverting outputs or high impedance outputs. 5
6 LOGIC DETAIL TO THREE OTHER A OR B INERTERS ONE OF 8 INERTERS DATA INPUT A OR B CC YA OR YB ENABLE A OR ENABLE B 6
7 PACKAGE DIMENSIONS PDIP N SUFFIX PLASTIC DIP PACKAGE CASE ISSUE E A 0 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. T SEATING PLANE G E F N K C D PL 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E BSC.27 BSC F G 0.00 BSC 2.54 BSC J K L BSC 7.62 BSC M N SOIC DW SUFFIX CASE 75D 05 ISSUE G H 0X 0.25 M B M D E A h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PLANE C L MILLIMETERS DIM MIN MAX A A B C D E e.27 BSC H h L
8 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 948E 02 ISSUE B 0.5 (0.006) T L U 2X L/2 0.5 (0.006) T U S PIN IDENT S C 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S S 0 A D G H B U J J N N K K ÍÍÍÍ ÍÍÍÍ SECTION N N F DETAIL E 0.25 (0.00) DETAIL E M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M
9 PACKAGE DIMENSIONS SOEIAJ F SUFFIX CASE ISSUE O e E H E 0 Z D A L E Q M L DETAIL P IEW P c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). b 0.3 (0.005) M A 0.0 (0.004) MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC H E L L E M Q Z
10 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. MC74HC244A/D
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